Verification IPs
Reduce Trunaround time & Faster SoC Design Verification
Verification IPs
MosChip’s verification IP’s reusable verification modules that consist of USB functional modules, traffic generators, protocol monitors, and functional coverage blocks. MosChip’s verification helps you accelerate the development of the verification process. MosChip has more than 30+ verification IPs. Our verification IP’s fit into every verification environment and support all simulators’ verification languages.
Interface IPs
USB2.0 Device BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which work on a parallel UTMI interface.
USB Host BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
This setup consists of an integrated upstream Host with Four-port HUB (DUT) downstream Devices of Full speed & Low speed, with strength modeling on Upstream Host port & Downstream Device ports for the emulation of the Host & Device dynamic attach & detach logic, It supports control, bulk, interrupt & isochronous transfers.
USB host BFM is a Verilog behavioral model, which is USB1.1 compliant and supports full & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
USB2.0 HUB BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high-speed full speed & low-speed USB transactions. It supports control, bulk, interrupt, isochronous and Split transactions, which works on a parallel UTMI interface.
The OVM compliant USB3.0 device OVC supports USB3.0 Device functionality. It consists of OVM verification capabilities like a sequencer, checker, and coverage metrics. The main functions of the USB3.0 device OVC are to perform USB3.0 device link training, link Initialization, link recovery, device enumeration, device data transfers with link flow control, and power management operations, packet formation/decoding is done by the device protocol layer and framing/de-framing is done by the device link layer.
PCIe model purchased from nSYS. This can be configured in either PCIe Root complex or endpoint mode. This model comprises PCIe checkers and monitors, which check the traffic flow and protocol violations.
USB2.0 Device BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which work on a parallel UTMI interface.
USB Host BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
This setup consists of an integrated upstream Host with Four-port HUB (DUT) downstream Devices of Full speed & Low speed, with strength modeling on Upstream Host port & Downstream Device ports for the emulation of the Host & Device dynamic attach & detach logic, It supports control, bulk, interrupt & isochronous transfers.
USB host BFM is a Verilog behavioral model, which is USB1.1 compliant and supports full & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
USB2.0 HUB BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high-speed full speed & low-speed USB transactions. It supports control, bulk, interrupt, isochronous and Split transactions, which works on a parallel UTMI interface.
The OVM compliant USB3.0 device OVC supports USB3.0 Device functionality. It consists of OVM verification capabilities like a sequencer, checker, and coverage metrics. The main functions of the USB3.0 device OVC are to perform USB3.0 device link training, link Initialization, link recovery, device enumeration, device data transfers with link flow control, and power management operations, packet formation/decoding is done by the device protocol layer and framing/de-framing is done by the device link layer.
PCIe model purchased from nSYS. This can be configured in either PCIe Root complex or endpoint mode. This model comprises PCIe checkers and monitors, which check the traffic flow and protocol violations.
Network IPs
Ethernet 10/100 verification IP
This BFM is a Verilog behavioural model, which is IEEE802.3 compliant and supports the 10/100 half/full duplex modes of operations. It can generate all types of packets and injects various error conditions
Communication IPs
This model implements the functionality of SPP, Nibble, Byte, ECP, ECP RLE, EPP modes and supports the faster data rates up to 2Mbytes/s. This IP sends and receives data based on the configuration settings using parallel port registers and stores the data for integrity checks.
This BFM is a Verilog behavioral model, which can operate in 4 different encoding/decoding modes of SIR/MIR/FIR/VFIR and so it has a division between them in its structure. The SIR encoding/decoding operates by using a standard UART as its controller.
This BFM is a Verilog behavioral model, which can generate SIR/MIR/FIR/VFIR frames to the USB1.1 host model and checks for the functional issues while receiving the IrDA frames from the USB host model. In transmit mode, the IrDA host application model prepares the IrDA frames based on the mode selection and sends them to the USB1.1 host verification IP, USB1.1 host interface model prepares the USB packets based on the IrDA frames and sends them to DUT.
Inter-Integrated-Circuit serial interface for connecting peripherals. Supports 100 Kbps-Standard mode, 400Kbps-Fast mode, 3.4 Mbps-High speed mode, and 5 Mbps-Ultra-fast-mode. If any of the modes are not supported. Current IP supports Master and Slave both.
This model implements RS-232 asynchronous transmit and receive logic. This model supports the baud rates from 50bps to 6mbps. This IP can be configurable for data width (5,6,7, and 8), stop bits (1 or 2), and parity (None, Even, Odd, mark, space).
This model implements the functionality of SPP, Nibble, Byte, ECP, ECP RLE, EPP modes and supports the faster data rates up to 2Mbytes/s. This IP sends and receives data based on the configuration settings using parallel port registers and stores the data for integrity checks.
This BFM is a Verilog behavioral model, which can operate in 4 different encoding/decoding modes of SIR/MIR/FIR/VFIR and so it has a division between them in its structure. The SIR encoding/decoding operates by using a standard UART as its controller.
This BFM is a Verilog behavioral model, which can generate SIR/MIR/FIR/VFIR frames to the USB1.1 host model and checks for the functional issues while receiving the IrDA frames from the USB host model. In transmit mode, the IrDA host application model prepares the IrDA frames based on the mode selection and sends them to the USB1.1 host verification IP, USB1.1 host interface model prepares the USB packets based on the IrDA frames and sends them to DUT.
Inter-Integrated-Circuit serial interface for connecting peripherals. Supports 100 Kbps-Standard mode, 400Kbps-Fast mode, 3.4 Mbps-High speed mode, and 5 Mbps-Ultra-fast-mode. If any of the modes are not supported. Current IP supports Master and Slave both.
This model implements RS-232 asynchronous transmit and receive logic. This model supports the baud rates from 50bps to 6mbps. This IP can be configurable for data width (5,6,7, and 8), stop bits (1 or 2), and parity (None, Even, Odd, mark, space).
Storage Interface
SATA Device application model
This BFM is a Verilog behavioural model, emulates the functionality of the device application model. The main functions of this model are to initialize SATA Device DUT, decode the commands and generate appropriate response to the DUT and storing the data for integrity checks.
SATA Host application model
This BFM is a Verilog behavioural model, emulates the functionality of the host application model. The main functions of this model are to initialize SATA Host DUT, create command and data structures, initiating the DUT, storing the data for integrity checks.
Display IP
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is a complaint of HDMI 1.1 specification. This BFM generates the video data, audio data, and auxiliary info-frames and transmits them on the TX lines.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is a complaint of HDMI 1.1 specification. This BFM generates the video data, audio data, and auxiliary info-frames and transmits them on the TX lines.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.