BRIDGING GAP BETWEEN INDUSTRY DEMANDS & ACADEMIC LEARNING
MosChip’s 100% subsidiary – Institute of Silicon Systems (ISS), is one of the established VLSI training institutes in India started by technocrats having 35+ years of VLSI industry experience. With a center in Hyderabad, Institute of Silicon Systems offers comprehensive industry-oriented training programs in Physical Design, Design Verification and Custom Layout. With the changes in the semiconductor industry landscape, the skill requirements of the industry have also changed drastically. The educational institutions in India with the static methods of teaching are not able to provide well-trained human resources as per the industry requirements. Updating the skill-set of the students as per the industry requirements has become mandatory.
Our training programs are designed to bridge the gap between the industry requirements and the student skill set. Our industry-focused training programs are designed and developed by the industry technocrats to focus on the overall development of the candidates by enhancing their behavioral and technical skills, making them job ready. Our courses lay emphasis on the fundamental knowledge of VLSI and how it can be used to implement best design practices.
In the short span of time, Institute of Silicon Systems has become a premier institute providing job-oriented VLSI training to students making them industry-ready engineers.
OUR COURSES:
ISS offers job-oriented courses designed by industry technocrats keeping in the mind the ever-growing skill set demand of the industry. Our list of courses includes:
Prerequisites for our courses:
B.E / B.Tech in ECE / EEE / M.E / M.Tech / M.S in VLSI /ES / DECS Minimum of 65% Aggregate.
i) Physical Design:
Duration of the course: 22 weeks
Course Details: Our Physical Design course is designed to cover the concepts of Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floorplanning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. Our students get to work on 5 to 6 different designs. The assignments are designed in such a way that our students have a clear understanding about handling the design from Synthesis to Sign-off within the given specification limits of Area, Timing and Power.
Tools used during training: Cadence – Encounter / Innovus, ETS / Tempus, RTL Compiler.
ii) Design Verification:
Duration of the course: 18 weeks
Course Details: Verification is a crucial step for companies. Before the IP goes to silicon process, it is important for the IPs to be error-free. Companies are spending a lot of money on the verification processes, which is resulting in an increase in demand of the verification engineers. ISS’s Design verification course prepares students to handle medium size IPs to complex IPs with ease. Our course covers Fundamental concepts in Digital abstraction, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Verilog, Verification Flows, Coverage Driven Verification concepts, System Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM flow.
Tools used during training: Cadence – Incisive Enterprise Simulator.
iii) Analog Layout:
Duration of the course: 13 weeks
Course Details: Our course covers MOSFET fundamentals, second-order effects, Digital logic gates, Fabrication concepts, Latch-Up, Analog building blocks, Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and STI effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC, and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks, and ESD path checks. Our students get to work on different kinds of layouts like Standard Cells, Level Shifter, Operational Amplifier, Band-gap, Digital to Analog Converter, Phase Locked Loop and SRAM.
Tools used during training: Virtuoso, PVS, Assura