Mixed - Signal IPs
One stop solution for custom/standard based interface
along with Link Layers | Integrating the IP into complex SOCs
Mixed - Signal IPs
MosChip’s PHY technology is based on G-Architecture which provides high-speed serial data interface (SerDes) IP which helps in developing low-cost, low-power SoC for various networking applications. The multi-lane multi-protocol Long Range (LR) PHY IP is part of MosChips’ high-performance multi-rate transceiver portfolio supporting up to 8Gbps, meeting the growing needs for small footprint, low-power consumption and low latency edge applications.
The PCI-Express IP consists of a digital PIPE interface and the mixed-signal transceiver core implements PCI-express 1.1, PCI-Express 2.1 and PCI-express 3.1 protocols. The IP supports various configurations such as endpoint and root complex and is suitable for a lot of applications. The PIPE layer is highly configurable and implements features such as skip insertions and deletion.
The STA PHY IP supports SATA 1 and SATA II standards and includes the configurable PCS layer. MosChip supplies XAUI transceiver for backplane connectivity. It implements protocols including CEI-6, CX4, and KX4, targeting a variety of networking SoC and supports a frequency range of 6.4G.
MosChip’s G-Architecture is ideal for supporting emerging standards like DisplayPort, HDMI, USB3.1, MIPI and other standards up to the data rate of 8G.
The PHY technology guarantees excellent interoperability with advanced jitter tolerance, frequency offset compensation, and linear receiver equalization techniques. Features such as built-in junction isolation rings reduce substrate noise and offer superior noise immunity.
The IP is silicon-proven in leading foundries and process technologies such as TSMC and Global Foundries and is available in wire-bond and flip-chip versions. The circuits use a low voltage supply and consume very minimal power.
Interface IPs
| IP Name | Standards | Details | Inquire |
|---|---|---|---|
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ADCSEQ12B3Ksps |
Ramping 12-bit ADC with SequencerNEW |
The ADCSEQ12B3Ksps is a digital sequencer attached to a small ramping 12-bit ADC at 3 Ksps. It sends multiple blocks of samples with different settings by block and is interfaced using SPI. |
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VSG3ST6 |
ARM HSSTP PHY with Link Layer NEW |
The VSG3ST6 is an enhanced simplex High-Speed STP macro with data transfer capabilities of up to 6.25/12.5Gbps. It includes a Standard ARM HS-STP simplex interface. In addition, on the same footprint using our technology, it can include a standard JTAG interface. |
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VHT1T28PF8 |
PCIE |
VHT1T28PF8 PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The VHT1T28PF8 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VHT1T28PF8 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension. |
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VSL312 |
PCIE GEN1/ GEN2 |
VSL312 PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The VSL312 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VSL312 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension. |
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VSL320 |
XAUI PHY |
VSL320 PHY supports up to 3.2G backplane applications. The benefit of this highly integrated PHY solution includes differentiated performance, simplified interoperability, and extensive built-in testability. |
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VSL330 |
CEI-6G-SR PHY |
VSL330 PHY supports up to 6.4G backplane applications. This comprehensive PHY family covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry. |
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VSL340 |
SATA PHY |
VSL340 PHY is suitable for both Host and Device applications within a Serial ATA system. The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a Serial ATA Link Layer where the 8b10b encoding and decoding of the data are done. Recovered data is provided using SATA-compliant D-word alignment. The SATA PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. |