Mixed Signal IPs

MosChip’s PHY technology is based on G-Architecture which provides high-speed serial data interface (SerDes) IP which helps in developing low-cost, low-power SoC for various networking applications. The PCI-Express IP consists of digital PIPE interface and the mixed-signal transceiver core implements PCI-express 1.1 and PCI-Express 2.0 protocols. The IP supports various configurations such as endpoint and root complex and is suitable for a lot of applications. The PIPE layer is highly-configurable and implements features such as skip insertions and deletion.

The STA PHY IP supports SATA 1 and SATA II standards and includes the configurable PCS layer. MosChip supplies XAUI transceiver for backplane connectivity. It implements protocols including CEI-6, CX4, and KX4, targeting a variety of networking SoC and supports a frequency range of 6.4G.

MosChip’s G-Architecture is ideal for supporting emerging standards like DisplayPort, HDMI, USB3.1, and others.

The PHY technology guarantees excellent interoperability with advanced jitter tolerance, frequency offset compensation, and linear receiver equalization techniques. Features such as built-in junction isolation rings reduce substrate noise and offer superior noise immunity.

The IP is silicon-proven in leading foundries and process technologies such as TSMC and Global Foundries and is available in wire-bond and flip-chip versions. The circuits use low voltage supply and consume very minimal power (<60mW at 3.125 GB/s).

Our Mixed signal IP’s are:

IP Standards Availability
TSMC Global Foundries
65nm G 65nm LP 28nm HPM 40nm LP 28nm HPP
VSL312 PCIE Gen1/ Gen2 Production Production Available Available Development
VSL320 XAUI PHY Production Production Available Available Development
VSL330 CEI – 6G-SR-PHY Production Production Available Available Development
VSL340 SATA PHY Production Production Available Available Development
VSG3ST6 ARM HSSTP PHY Available Available Available Available Development