Analog Layout Services

Over the last 29+ years, MosChip has been involved in layouts on many analog and mixed-signal chips. MosChip has been involved in tape outs targeted to 14nm/10nm/7nm process nodes. MosChip team has experience with TSMC, Global and Samsung Foundries. The MosChip team has expertise in handling layouts on high-frequency PLLs. The team has expertise in SerDes, PMUs, RF designs, Memories, Data Converters, and IOs.

Expertise

  • Block level and full chip layouts
  • Floor planning, Placement, Routing
  • Matching transistor pairs
  • Shielding critical nets
  • EM&IR analysis and repair
  • DRC/LVS
  • Expertise in Data Converters, IOs, Clocking Circuits (PLL, DLL), Serdes, Memories, PMUs and RF layouts
  • Foundries: Expertise in TSMC, UMC, Global Foundry, IBM, Tower Jazz, X-Fab, Micrel, Dongbu and Samsung
  • Process Nodes: 500nm all the way down to 16nm/14nm/10nm/7nm
  • Expertise in Bulk CMOS, SOI and BCD processes

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