Analog Layout

Over the last few decades, MosChip has been involved in layouts on a large number of analog and mixed-signal chips. MosChip has been involved in tape outs targeted to 14nm/10nm/7nm process nodes. MosChip team has experience with TSMC, Global and Samsung Foundries. The moschip team has expertise in handling layouts on high-frequency PLLs. The team has expertise in PMUs, RF designs, Memories, Data Converters, and IOs.

Expertise:

  • Floor planning, Placement, Routing
  • Matching transistor pairs
  • Shielding critical nets
  • EM&IR analysis and repair
  • DRC/LVS
  • Expertise in Data Converters, IOs, Clocking Circuits (PLL, DLL), Serdes, Memories, PMUs and RF layout Foundry
  • TSMC, UMC, Chartered/Global Foundry, IBM, Tower Jazz, X-Fab, Micrel, Dongbu, Samsung Process Nodes
  • 500nm all the way down to 16nm/14nm/10nm/7nm
  • Expertise in Bulk CMOS, SOI and BCD processes

Tools:

Task Vendors and Tools
Layout Cadence, Virtuoso-L, Virtuoso-XL
Physical Verification Mentor, Calibre
Synopsys, Hercules
Cadence, Assura, PVS
EM & IR Ansys Totem