RTL Design and Design Verification
MosChip offers wide range of RTL design and designs verification services. With more then 16+ years of experience MosChip has emerged as a leader in RTL Design and Design Verification services with in-house capabilities in IP verification, Block/Sub-system-level verification with multiple clocks, power domains and speed upto 1.2GHz.
Apart from these our expertise on RTL design, FPGA devices, and associated tool flow; SoC verification languages (HVL); ASIC Prototyping and post-silicon validation combined with a strong understanding of peripheral system level deployment and industry standard verification helps our clients build error-free design and reduce the time-to-market.
MosChip has proven to be a valuable partner to various businesses in turnkey verification ODCs for semiconductor product companies globally. Combining our expertise in ASIC design and design verification, MosChip also offers a portfolio of custom verification IPs for standard interfaces for various industries.
- IP/SoC Design and Verification
- Expertise in developing verification testbench components for chip/module level using Verilog/System Verilog/C/C++
- Expertise in verification methodologies like eRM/OVM/UVM to develop extendable test-bench/test-cases environment.
- Microarchitecture development
- Test Plan, Test Bench Development, Development of BFMs, Monitors, Checkers Block level, Sub-system level, and SoC-level verification
- Defining and executing detailed verification plan from spec working with architects, designers, system engineers.
- Writing tests, debugging tests, automating regression scripts and regression environment.
- Incorporating code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tape out.
- Functional and Code Coverage Analysis
- Low Power Verification (CPF/UPF flows)
- Gate Level Simulations
- Expertise in PCI-E 1-3, USB 2/3, DDR 2/3/4, SATA, HDMI, AHB, APB, AXI, SPI, I2C, UART, I2S, ARM Cortex A53, A15, A7, Gigabit Ethernet
|Task||Vendors and Tools|
|Design Audit (Lint, CDC)||Synopsys, Spyglass|