Digital IPs
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Digital IPs
MosChip has more than 30+ IP digital in its portfolio. We provide digital verification IPs and validation services ranging from analog, mixed-signal, ASIC, SoC, digital logic, and custom IP. We use advanced verification methods for projects as per the client’s process.
Network IPs
Ethernet 10/100 MAC
Ethernet controller is compliant to IEEE802.3 and it provides interface between the host subsystem and the Media Independent Interface (MII). The 10/100 Ethernet MAC consists of DMA (TX DMA, RX DMA), TLI (TX buffer, RX buffer), 10/100 Ethernet controller. The DMA automates data transfers and frees the CPU from this task. The Transaction Layer Interface (TLI) is a 64-bit wide block designed to provide a bridge between the DMA controller and a 10/100 Ethernet controller. The TLI uses 4 Kbytes FIFO for transmit (TX Buffer) and 2 Kbytes FIFO for receive (RX Buffer).
Interface IPs
The USB 2.0 Host Controller implements an EHCI interface and OHCI interface that interfaces UTMI USB port transceiver on one side and to an application device core/system’s microprocessor on the other side using VCI interface. The EHCI controller is used for all high-speed communications to high-speed-mode devices connected to the root port.
USB 2.0 Device controller implements a complete high/full speed peripheral controller that interfaces UTMI USB port transceiver on one side and to an application device core/system’s microprocessor on the other. It supports control, bulk, interrupt and isochronous transfers defined by USB2.0 specifications.
On-The-Go Controller (OTG) is a USB2.0 OTG supplement compliant with support of high-, full-, and low-speed operation. It supports a UTMI interface to connect to a USB OTG PHY. It uses a VCI bus to interface with an application device core/system’s microprocessor external processor.
USB device controller (UDC) works like a source and destination of data for the USB host controller. USB device protocol is implemented in this controller. This controller will respond to all standard commands specified in the USB1.1 specification. This is compliant with the USB1.1 specifications. Have the clock recovery mechanism to recover the clock from the data on dp and dm lines and 48MHz external clock.
USB3.0 Host controller IP is compliant to xHCI specifications 0.96 and capable of supporting SuperSpeed, High Speed, Full Speed, and Low-Speed devices. The Host Controller IP supports the parallel operation of Super Speed and USB2.0 on Root Hub Ports. Host controller supports all USB3.0 and USB2.0 Link Power Management features. The Host Controller IP provides a simple VCI interface to connect to any System Bus.
The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3. It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths. The application interface can be configured of 32 bit as well as a 64-bit interface as per requirements. The IP supports both master and slave operations and PCI power management.
The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1. PCI Host Bridge contains an internal arbiter to manage up to 4 external devices.
The USB 2.0 Host Controller implements an EHCI interface and OHCI interface that interfaces UTMI USB port transceiver on one side and to an application device core/system’s microprocessor on the other side using VCI interface. The EHCI controller is used for all high-speed communications to high-speed-mode devices connected to the root port.
USB 2.0 Device controller implements a complete high/full speed peripheral controller that interfaces UTMI USB port transceiver on one side and to an application device core/system’s microprocessor on the other. It supports control, bulk, interrupt and isochronous transfers defined by USB2.0 specifications.
On-The-Go Controller (OTG) is a USB2.0 OTG supplement compliant with support of high-, full-, and low-speed operation. It supports a UTMI interface to connect to a USB OTG PHY. It uses a VCI bus to interface with an application device core/system’s microprocessor external processor.
USB device controller (UDC) works like a source and destination of data for the USB host controller. USB device protocol is implemented in this controller. This controller will respond to all standard commands specified in the USB1.1 specification. This is compliant with the USB1.1 specifications. Have the clock recovery mechanism to recover the clock from the data on dp and dm lines and 48MHz external clock.
USB3.0 Host controller IP is compliant to xHCI specifications 0.96 and capable of supporting SuperSpeed, High Speed, Full Speed, and Low-Speed devices. The Host Controller IP supports the parallel operation of Super Speed and USB2.0 on Root Hub Ports. Host controller supports all USB3.0 and USB2.0 Link Power Management features. The Host Controller IP provides a simple VCI interface to connect to any System Bus.
The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3. It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths. The application interface can be configured of 32 bit as well as a 64-bit interface as per requirements. The IP supports both master and slave operations and PCI power management.
The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1. PCI Host Bridge contains an internal arbiter to manage up to 4 external devices.
Memory Controlled IP
DMA Controller
The memory 2 memory DMA controller transfers data from memory location to other memory location. DMA operation begins when software enables a DMA, after setting the source and destination starting addresses, transfer count, and control information. The DMA engine moves the data block and the DMA operation ends naturally when the number of bytes specified by the transfer count has been moved.
Communication IPs
The IRDA controller supports data rates from 2.4 Kbps to 115.2Kbps in SIR mode, 1.152 Mbps in MIR (Medium IR), and 4Mbps in FIR mode.
The I2C (Inter-Integrated Circuit) master controller operates using two wires – SCL and SDA. The controller supports programmable speeds up to 400 kHz. It has a generic application interface for integration.
The SPI (Serial Peripheral Interface) host controller supports a maximum of 4 devices and has a programmable SPI clock. This supports full-duplex synchronous data transfers. The controller supports a variable length of transfer word up to 32 bits and supports programmable SPI Clock Polarity and Phases.
The Serial Port IP is Single Port Standalone IP, which supports all the features in the modes like 16C450, 16C550, 16C550Ex, 16C650, 16C750/16C950. Supports bi-directional speeds from 50 bps to 16 Mbps per serial port. Supports full serial modem control. Supports Hardware as well as Software flow control.
The IEEE1284 compliant parallel port controller supports faster data rates up to 2.0Mbytes/sec. Supports Nibble mode, Byte Mode, EPP, ECP. Auto-negotiation is implemented in hardware.
General Purpose I/O pins are used for system control and connection of various devices. This (GPIO) controller provides dedicated general-purpose pins that can be configured as either inputs or outputs. There can be 32 (programmable*) General Purpose Input/output pins. All the GPIO pins in input mode can generate interruptions. Each GPIO can be configured independently of all other GPIO. The GPIO’s allow data input and IRQ generation.
The IRDA controller supports data rates from 2.4 Kbps to 115.2Kbps in SIR mode, 1.152 Mbps in MIR (Medium IR), and 4Mbps in FIR mode.
The I2C (Inter-Integrated Circuit) master controller operates using two wires – SCL and SDA. The controller supports programmable speeds up to 400 kHz. It has a generic application interface for integration.
The SPI (Serial Peripheral Interface) host controller supports a maximum of 4 devices and has a programmable SPI clock. This supports full-duplex synchronous data transfers. The controller supports a variable length of transfer word up to 32 bits and supports programmable SPI Clock Polarity and Phases.
The Serial Port IP is Single Port Standalone IP, which supports all the features in the modes like 16C450, 16C550, 16C550Ex, 16C650, 16C750/16C950. Supports bi-directional speeds from 50 bps to 16 Mbps per serial port. Supports full serial modem control. Supports Hardware as well as Software flow control.
The IEEE1284 compliant parallel port controller supports faster data rates up to 2.0Mbytes/sec. Supports Nibble mode, Byte Mode, EPP, ECP. Auto-negotiation is implemented in hardware.
General Purpose I/O pins are used for system control and connection of various devices. This (GPIO) controller provides dedicated general-purpose pins that can be configured as either inputs or outputs. There can be 32 (programmable*) General Purpose Input/output pins. All the GPIO pins in input mode can generate interruptions. Each GPIO can be configured independently of all other GPIO. The GPIO’s allow data input and IRQ generation.
Storage Interface
SATA II v2.6 Host Controller
The SATA II Host Controller implements an AHCI/Emulation interfaces that interfaces with SATA PHY using SAPIS interface on one side and to an application on the other side using VCI interface. Emulation interface is used to backward compatible with existing software and supports both PIO and DMA modes of operation. AHCI is Advanced Host Controller Interface, which is a hardware mechanism that allows software to communicate with Serial ATA devices. It supports PIO, DMA and FPDMA modes of operation and supports NCQ using FPDMA mode. It has aggressive power management capabilities.
SATA II v2.6 Device Controller
The SATA II Device Controller interfaces with SATA PHY using SAPIS interface on one side and to an application on the other side using VCI interface. It supports PIO, DMA, QDMA, FPDMA modes of operation and supports NCQ using FPDMA mode of operation. It also supports SATA power management features.
AMBA Bus
VCI to AHB bus bridge controller is a protocol converter that accepts the transaction from the VCI master and converts it into equivalent AHB transactions. This bridge accepts all valid VCI byte enables and VCI transactions can be any length. VCI I/F is a 64-bit interface, AHB I/F is a 32- or 64-bit interface it is a programmable option.
This converts 64-bit AHB transactions into multi 64-bit transactions.
This converts a single 32-bit AHB transaction into multi 32-bit AHB transactions.
VCI to AHB bus bridge controller is a protocol converter that accepts the transaction from the VCI master and converts it into equivalent AHB transactions. This bridge accepts all valid VCI byte enables and VCI transactions can be any length. VCI I/F is a 64-bit interface, AHB I/F is a 32- or 64-bit interface it is a programmable option.
This converts 64-bit AHB transactions into multi 64-bit transactions.
This converts a single 32-bit AHB transaction into multi 32-bit AHB transactions.
Display IP
HDMI Transmitter is a compact audio/video interface for transmitting uncompressed digital data. It takes 24-bit video data and SPDIF/I2S audio data from respective sources and sends it over the HDMI interface. It has provided an I2C interface used to read the capabilities of a SINK. It has an HDCP engine to encrypt video/audio data being transmitted.
HDMI Receiver is a compact audio/video interface for receiving uncompressed digital data. It receives 30-bit video and audio data along with control information interleaved into HDMI packets on 3 HDMI channels and sends it over video (RGB interface) and audio (SPDIF/I2S interface). It has an HDCP engine to decrypt video/audio data is received. It has an I2C channel to provide receiver capabilities information to the transmitter.
HDMI Transmitter is a compact audio/video interface for transmitting uncompressed digital data. It takes 24-bit video data and SPDIF/I2S audio data from respective sources and sends it over the HDMI interface. It has provided an I2C interface used to read the capabilities of a SINK. It has an HDCP engine to encrypt video/audio data being transmitted.
HDMI Receiver is a compact audio/video interface for receiving uncompressed digital data. It receives 30-bit video and audio data along with control information interleaved into HDMI packets on 3 HDMI channels and sends it over video (RGB interface) and audio (SPDIF/I2S interface). It has an HDCP engine to decrypt video/audio data is received. It has an I2C channel to provide receiver capabilities information to the transmitter.
Misc. IP
Random Number Generator
The random number generator f\generates true random numbers using a LFSR. The LFSR can only be read by the internal CPU.