Getting started with RISC-V and its Architecture
Due to high computing demands, SoCs are becoming more complex. AI and Machine Learning, Multimedia, and connectivity are critical factors for this. When developing an SoC, the critical decision to be made is choosing the proper Instruction Set Architecture (ISA) and the processor hardware architecture. There are many ISAs available having different pros and cons. Some of them are proprietary and licensable, while some of them are open. ARM and x86 architectures dominate many computing markets, while RISC-V has emerged as a rapidly growing open ISA in processor architectures.
There are different variants of architectures provided by vendors. Significant benefits of using licensed architecture are already developed software and a ready-to-use ecosystem. However, design flexibility is minimal with these architectures. Open-source ISAs offer greater flexibility, and they are free. Having an open-source ISA also makes room for continuous improvements. People can modify them as per their requirements and contribute back to make them better.
RISC-V (Reduced Instruction Set Computing) is an open standard instruction set architecture based on Reduced Instruction Set Computing (RISC) principles. The RISC-V architecture project was started in 2010 by Prof. Krste Asanović, Prof. David Patterson, graduate students Yunsup Lee and Andrew Waterman at the UC (University of California, Berkeley).
RISC-V is a royalty-free, license-free, and high-quality ISA set. The RISC-V standards are maintained by the RISC-V International Company. RISC-V International is a non-profit organization formed in Aug 2015 to maintain its standards publicly. Currently, more the 4000+ members across more than 70 countries have joined RISC-V International. The RISC-V ISA specifications are openly published and available under permissive licensing. Well, the RISC-V is neither a company nor a CPU implementation.
How is RISC-V different than other processors?
Freely available
Unlike other ISA designs, the RISC-V ISA is provided under free licensing, which means that without paying any fees, we can still use, modify, and distribute it.
Open Source
As the RISC-V ISA is open source, people can use it and improve it. This makes the product more reliable.
Fully Customizable
Though there may be different proprietary processor cores, customization is not possible based on the requirement. The advantage of using the RISC-V ISA (Instruction Set Architecture) is that it enables companies to develop a completely customizable product, specifically to their requirements. They can start with the RISC-V core and add whatever is based on their need. This ultimately saves them time and money, resulting in low-cost and low-power products which can be used for a long time.
Support for user-level ISA extensions
RISC-V is very modular. There are many standard extensions available for specific purposes which can be added to the base as per requirement. Developers can also create their non-standard extensions. Some of the standard extensions used by RISC-V are:
- M – Integer Multiplication and Division
- I – Integer
- A – Atomics Operation
- F – Single-Precision Floating Point
- D – Double-Precision Floating Point
- Q – Quad-Precision Floating Point
- G – General Purpose, i.e., IMAFD
- C – 16-bit Compressed instructions
- B – Bit Manipulation
- V – Vector Extension for data-parallel processing and AI workloads
Designed 32/64/128 bits wide support
RISC-V has different bit-width support, providing more flexibility for product development.
Beyond its configurable architecture, RISC-V provides multicore support and virtualization capabilities for hypervisor development, making it well suited for scalable hardware design across embedded, industrial, automotive, and data center applications.
RISC-V supports different software privileged levels
- User Mode (U-Mode) – Generally runs user processes
- Supervisor Mode (S-Mode) – Kernel (Including kernel modules and device drivers), Hypervisor
- Machine Mode (M-Mode) – Bootloader and Firmware
The processor can run in only one of the privilege modes at a time. The machine mode is the highest privileged mode and the only required mode. The privilege level defines the capabilities of the running software during its execution. These different levels of modes make RISC-V a choice for certain & safety products.
One thing to note is that RISC-V is an open-source Instruction Set Architecture. Using this architecture, anybody can develop processor cores. Developed cores can be free or proprietary depending on the choice of who develops them.
RISC-V can be used for a variety of applications because of its great flexibility, extensions, and possible customization. RISC-V is suitable for all types of micro-processing systems to supercomputing systems. It can fit into small memory devices, consuming less memory & power. Similarly, its other variant can provide high computing capabilities. Its privileged architecture and optional security extensions support secure execution, trusted firmware, and hardware-based isolation.
Some of the applications suited for RISC-V are:
- AI and Machine Learning edge inference
- Security solutions
- IoT
RISC-V for AI and Machine Learning Edge Inference
AI and Machine Learning inference has become a core workload for many edge devices, from industrial systems and smart cameras to automotive platforms and intelligent IoT gateways. These applications require processors that can deliver high performance while operating within strict power, memory, and cost constraints. RISC-V enables developers to tailor processors for these workloads by selecting only the required ISA extensions and implementing custom instructions or AI accelerators where needed.
RISC-V for Security Solution
MosChip has used RISC-V MC CPU soft IP to develop security solutions. The diagram below illustrates it in brief.
In Safety-critical products, RISC-V works as the root of trust to ensure the authenticity and integrity of the firmware. It provides below functionalities:
- Protect platform firmware & critical data: It protects platform firmware and critical data from unauthorized access.
- Ensure authenticity & integrity of Firmware: On boot, it checks for firmware signature and verifies that it is not tempered.
- Detect corrupted platform firmware & critical data: It checks platform firmware & critical data on boot and runtime when requested. If the platform or critical data gets corrupted for any reason, it can detect them and take corrective actions.
- Restore corrupted platform firmware and/or critical data: If platform firmware or critical data are corrupted, it performs restoration of platform firmware and/or critical data from the backup partition based on the requirement.
- Runtime monitoring for unintended access: During runtime, it monitors bus traffic accessing secure memories (e.g., SPI traffic) and blocks unintended access.
RISC-V for IoT solution
The gateway is developed with a RISC-V-based MCU to leverage the security features provided by RISC-V.
The gateway is developed to perform device management, user management, and services management. A cloud agent is developed to handle all the cloud activity from device to cloud via the gateway. A device agent is developed to manage all the devices connected to the gateway. A service agent makes sure of all the interfaces and the status of the interface and connected device.
MosChip brings strong expertise across product engineering and hardware design services for RISC-V-based platforms. The expertise spans FPGA board bring-up for RISC-V cores, OS porting for customized RISC-V platforms, and enablement across Linux, RTOS, and bare-metal environments. MosChip also supports driver development, integration, and porting for interfaces including SPI, I2C, GPIO, PLIC, CLINT (MTIME), and MMC. In addition, we support performance benchmarking and validation for RISC-V implementations across embedded systems.
FAQs
A RISC-V ISA defines the instruction set that software uses to communicate with hardware. A RISC-V processor is a hardware implementation of that ISA. Multiple processors can implement the same RISC-V specification while targeting different applications and performance requirements.
RISC-V follows a modular architecture that allows developers to implement the standard ISA extensions required for their application. It also provides the option to add custom instructions for application-specific workloads while preserving compatibility with the base ISA.
Yes. RISC-V supports different processor configurations, ranging from low-power embedded implementations to processors designed for higher computing requirements. The configuration depends on the application and the processor implementation.
RISC-V processors can support different operating systems depending on their implementation. Commonly supported software environments include Linux, Zephyr RTOS, FreeRTOS, and bare-metal applications.
A modular ISA allows developers to implement only the instruction set extensions required for a particular application. This provides flexibility when designing processors for different performance, power, and functionality requirements.
In hardware design, RISC-V can be implemented as a processor core within an SoC or FPGA-based platform. Designers can select the required ISA extensions, integrate peripherals, and develop processor implementations based on the needs of the target application.
