PoV on Understanding the Shift Towards Chiplet Architecture in SoC Design
As SoC designs scale, they must integrate more compute, memory, and specialized functionality. Scaling a monolithic die is becoming increasingly challenging. Die size, manufacturing yield, process-node requirements, and the cost of developing increasingly complex designs are pushing the industry to look at alternative approaches to system integration. Chiplet architecture addresses these challenges by dividing a complex system into multiple smaller dies integrated within a single package.
The approach also offers flexibility when merging different functions, various process technologies, and fast interfaces. As packaging technologies and die-to-die interconnect standards grow more mature, chiplets are becoming an important part of the discussion around how future SoCs will be built and scaled.
1. Why is chiplet architecture gaining momentum in SoC design today?
Chiplet architecture momentum is mainly driven by system needs. While the need to integrate faster & denser memory close to the processing elements led to HBM memory, the need for scaling out led to interfaces like UCIe. Systems requiring modular heterogeneous integration leverage Chiplet architecture. Chiplets get integrated through an interposer within the package, which will maximize the data exchange rate between components. All these factors are driving the momentum.
2. How do you decide which functions should be separated in a chiplet architecture?
Modularity of the system defines the individual chiplet architecture. For example, in scale-out systems, the repetitive functions go into the individual chiplets. In case of systems where we see many high-speed interfaces that remain unchanged across multiple SKUs of products, the high-speed interfaces are grouped into one chiplet. In systems with larger heterogeneous functionalities (example CPU complex and GPU complex), those heterogeneous functions can be implemented through individual chiplets.
3. What are the biggest advantages of chiplet architecture over a monolithic SoC?
As we pack more functionality onto one package, the reticle size will become a limiting factor for a monolithic SoC; chiplets address this exact issue. Monolithic SoCs lack the capability to divide and conquer complex functionality into manageable pieces. Chiplets reduce the need to re-spin a bigger functional die. Functionality that needs frequent upgrades can be implemented on a separate chiplet.
4. What are the key technical challenges in making a chiplet architecture work as one system?
Though many of the factors have been fairly well tackled to date, here are the complexities involved:
- Chip-on-Wafer-on-Substrate (CoWoS) packaging, where multiple chiplets are integrated through an interposer, introduces challenges around high-density connections and package-level integration.
- Managing SI/PI across chiplets, as high-speed communication between chiplets requires careful management of signal integrity and power integrity across the die-to-die interconnects to ensure reliable system-level operation.
- Silicon interposer-related issues due to heterogeneous thermal impacts on different chiplets (Coefficient of Thermal Expansion), cracks in microbumps, and physical warpage.
- KGD testing and yield-related issues. Each individual die test coverage gap gets compounded into the overall package yield.
5. How does chiplet architecture influence packaging and die-to-die interconnects?
Chiplet packaging will need either interposer- or TSV-based packaging. Depending on the platform requirements, 2.5D or 3D stacking is chosen. A 2.5D package that requires an interposer will need all the IOs to be microbumps, which are smaller in size than regular bumps. Through-Silicon Vias (TSVs) are more common for 3D stacking. All the interface IOs need to support microbumps. There are multiple die-to-die interconnection standards that have evolved to enable chiplet architectures. Open HBI (used for HBM), UCIe, NVIDIA’s NVLink, AMD’s Infinity Fabric, etc., have evolved and are continuously being upgraded to support Chiplet packaging.
6. Where do you see chiplet architecture heading over the next few years?
With the 3nm and 2nm die costing and yield concerns on larger die sizes in smaller technologies, the Chiplet architecture is bound to become the de facto packaging for chips with larger & more complex functionality. With open standards like UCIe becoming more mature, the adoption rate will definitely increase manifold in the next few years.
Making chiplet-based designs work requires engineering across multiple stages, from defining the right partitioning strategy and integrating high-speed interfaces to verification and post-silicon validation.
MosChip supports complex SoC design from RTL through volume production, with capabilities spanning turnkey ASIC and SoC design, verification, physical design, DFT, analog-mixed-signal design, high-speed interfaces, and post-silicon validation. These capabilities extend to chiplet architecture and integration, die-to-die interfaces, UCIe-based connectivity, and 2.5D packaging considerations, supporting the different engineering requirements involved in developing complex and heterogeneous semiconductor architectures.
