Memory-Aware ASIC Design for AI Workloads
Recently, AI processors have seen significant improvements in computing power due to specialized units such as NPUs…
Author: Siva Raghu Ram Voleti
Siva Raghu Ram Voleti is Vice President, ASIC Design at MosChip Technologies, with 25+ years of experience in Silicon design and SoC development. His expertise spans End to End Chip delivery, SoC architecture, design, verification, and front-end development, with extensive experience in multimedia SoCs and Storage controllers. He has led multiple successful SoC programs and worked closely with customers on technical specifications and product definition. His experience also includes back-end and foundry interfacing, along with building and leading high-performing engineering teams.
