POV on Top Considerations for Designing AI Inference Chips
AI inference workloads are becoming more compute-intensive, with higher demands on throughput, memory access, and power…
Author: Jyoti Kaushik
Jyoti Kaushik is Associate Vice President of Physical Design at MosChip and has over 26 years of VLSI industry experience in senior leadership and technical roles at industry-leading semiconductor companies.
As an engineering leader, he has led ASIC Design for diverse domains, including AI, Automotive, Audio, Processors, Programmable logic, Networking, Vision and Secure hardware.
At MosChip, he leads the Physical Design team. Jyoti holds a Degree in Electronics from MD University, Haryana and a Masters in Signal Processing from NSIT (Delhi University).
