Author: Jigar Mori

Jigarkumar Mori is a Senior Manager in FPGA/ RTL Design at MosChip. He has 14 years of experience specializing in FPGA and RTL design, VHDL, Verilog, MATLAB, Simulink, computer vision, and deep learning development. As a skilled engineer, he has developed expertise in designing and implementing Xilinx and Lattice FPGA-based systems, programming languages such as VHDL and Verilog to optimize performance and efficiency. My proficiency in MATLAB and Simulink has allowed me to develop sophisticated algorithms and models, pushing the boundaries of what's possible in computer vision and deep learning applications.