Domain
Challenge
Enable always-on voice recognition on low-power FPGA devices while working within strict power, memory, and compute constraints. Maintaining continuous listening without draining system resources was critical for edge and embedded applications.
Solution
A custom lightweight neural network for key phrase recognition, delivered as a pre-trained, fully documented reference model with training pipelines, deployment steps, and a live demonstration on the Lattice iCE40 FPGA.
Platform
Lattice iCE40 FPGA, Lattice sensAI, TensorFlow, Python, C++, Ubuntu/Linux
A leading U.S.-based semiconductor company specializing in low-power FPGAs partnered with MosChip to design a custom neural network for key phrase recognition, drawing on ours edge AI development services. The goal was a reference model that customers could use as a foundation to build and deploy AI-powered, always-on voice control on their own FPGA devices.
MosChip designed, trained, and deployed the model on the Lattice iCE40 FPGA, keeping this edge AI solution lightweight, power-efficient, and reusable across applications. Alongside the model, MosChip delivered full documentation, training pipelines, deployment steps, and binary creation workflows, so customers could adopt, customize, and scale their own voice-enabled solutions without deep FPGA or neural network expertise.
THE RESULT
The outcome is a ready-to-use, pre-trained model and a robust reference framework that helps businesses across computing. Consumer electronics, automotive, and home automation accelerate AI adoption with FPGA-based, voice-enabled systems.
Bringing AI-powered voice recognition to low-power FPGAs meant tackling four problems at once, each of which slowed customers down in a different way:
Addressing these challenges requires more than just a compact AI model. Customers needed a validated framework that simplified model deployment, reduced development effort, and made AI on low-power FPGAs easier to adopt and scale.
MosChip designed and developed a custom Key Phrase Recognition solution for low-power FPGA devices, enabling always-on voice recognition within limited power, memory, and processing resources. The solution provides a reusable foundation for voice-enabled applications and simplifies AI deployment on resource-constrained hardware. The engagement covered five areas:
Voice data is used to train the key phrase model, which is converted with the Lattice compiler and TFLite converter into a quantized model. On the FPGA, the device listens continuously at low power, pre-processes incoming speech, runs the quantized model, and raises an alert when a key phrase is detected.
| Component | specification |
|---|---|
| Hardware Platform | Lattice iCE40 FPGA, HiMax HM01B0 UPduino shield |
| AI Frameworks | TensorFlow, cuDNN, Anaconda, TFLite conversion |
| FPGA Toolchain | Lattice Radiant v1.1, Lattice Radiant Programmer v1.1, Lattice sensAI Compiler v2.1 |
| Programming Languages | Python, C++ |
| Operating System | Ubuntu/Linux |
| Deployment Format | Quantized model compiled to FPGA binary |
By pairing a purpose-built, FPGA-optimized model with complete documentation and pipelines, MosChip gave the client something customers can build on well beyond a single use case.
Key phrase recognition detects specific spoken words or phrases, such as “machine on” or “machine off,” and triggers a defined action when one is heard. It powers always-on voice control in smart home devices, consumer electronics, industrial equipment, automotive systems, and IoT products, where a small, fast, power-efficient model is needed rather than full speech-to-text.
Running recognition directly on the device keeps latency low, avoids sending audio off the device, and works without a network connection. A low-power FPGA can listen continuously within a very small power budget, which makes it a good fit for battery-powered and always-on products.
Popular neural networks are typically designed for GPUs or powerful processors and require more memory, computing power, and energy than small FPGAs can provide. To run efficiently, models need to be purpose-built or optimized, then quantized and compiled to fit within the FPGA’s limited DSP, memory, and power resources.
A pre-trained, documented reference model gives teams a working starting point. They can use it as-is, retrain it on their own voice data, or extend it to new phrases, instead of building the neural network, training pipeline, and deployment flow from scratch. This shortens the learning curve and reduces time to market.

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