ASIC RTL Engineer Requirements Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC….
Design Verification Engineer Requirements Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage,…
STA Engineer Requirements Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of <14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Job Specifications
