The ADCSEQ12B3Ksps is a digital sequencer attached to a small ramping 12-bit ADC at 3 Ksps. It sends multiple blocks of samples with different settings by block and is interfaced using SPI.
The VSG3ST6 is an enhanced simplex High-Speed STP macro with data transfer capabilities of up to 6.25/12.5Gbps. It includes a Standard ARM HS-STP simplex interface. In addition, on the same footprint using our technology, it can include a standard JTAG interface.
VHT1T28PF8 PHY is suitable for both Root Complex and End Point applications within a PCI Express (Gen3) system. The VHT1T28PF8 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VHT1T28PF8 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension.
VSL312 PHY is suitable for both Root Complex and End Point applications within a PCI Express (Gen 1/Gen 2) system. The VSL312 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VSL312 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension.
VSL320 PHY (XAUI) supports up to 3.2G backplane applications. The benefit of this highly integrated PHY solution includes differentiated performance, simplified interoperability, and extensive built-in testability.
VSL330 PHY (CEI-6G-SR ) supports up to 6.4G backplane applications. This comprehensive PHY family covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry.
VSL340 PHY is suitable for both Host and Device applications within a Serial ATA system. The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a Serial ATA Link Layer where the 8b10b encoding and decoding of the data are done. Recovered data is provided using SATA-compliant D-word alignment. The SATA PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products.
