DIGITAL IP
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USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes. Support PIPE and UTMI+/ULPI interfaces with full link power management. The clock domain crossing mechanism between USB and xHCI/system-bus logic provides flexibility for easy integration. 

• AMBA-AXI system-bus interface for configuration-space access and data-path interface
• Bulk-stream for USB Attached SCSI Protocol (UASP) transfers
• Up to 16 IN and OUT Endpoints including control Endpoint
• Sideband interrupt and message signal interrupts
• Precision Time Measurement (PTM)

USB 3.2 Dual Role Device (DRD) softcore semiconductor IP is designed for applications requiring both USB Host and Device implementation. This core comprises USB3.2 SSP, SS, HS/FS/LS Host, and Device controllers in a single codebase that supports role-swap functionality

• eXtensible Host Controller Interface with USB protocol-layer, and link-layers implementation. USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes
• Support PIPE and UTMI+/ULPI interfaces with full-link power management
• AMBA-AXI system-bus interface for configuration-space access and data-path interface
• Up to 16 IN and OUT Endpoints including control Endpoint
• Parameterized design allows configuration of internal buffers based on application needs
• Clock domain crossing mechanism between USB and system-bus logic provides flexibility for easy integration

USB 3.2 Retimer softcore is designed for use in USB Port/Cable Retimer applications with USB SuperSpeed Plus/SuperSpeed link operations. The IP has been verified in simulation and is synthesis clean for FPGA implementations 

• SuperSpeed Plus @10Gbps with fallback to SuperSpeed @5Gbps
• USB-Link parallel data-path 20bit for SS, and 32bit for SSP
• Implements Digital-PHY PCS as part of the core supporting 8b/10b and 128b/132b codec with scrambler and descrambler, error detection-correction, Clock offset compensation with elasticity buffer, LFPS, full LPM, and compliance-mode
• Easy customization for interface to PMA/SERDES logic and sideband signalling

The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1. PCI Host Bridge contains an internal arbiter to manage up to 4 external devices 

SHA-1 IP core implements Secure Hash Algorithms specified in FIPS 180-4 standard. Common cores are available for ASIC and FPGA applications. 

• IP core supports higher frequency and accepts data every 41 or 21 clocks as opposed to every 80 clocks for IPs available in the market.
• SHA1 supports SHA1 as per FIPS 180-4
• 64-bit or 128-bit data path interface
• Padding is added as per the specification to make the message a multiple of 512-bit block
• SHA1 produces a message digest of 160 bits
• Accepts a new block every 41 clocks (64-bit data path) or 21 clocks (128-bit data path)
• Fully synchronous design 

SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach. The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard. A common core is available for diverse ASIC & FPGA applications. It ensures data integrity and/or user authentication in a range of applications, including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.

• Compliant with NIST’s FIPS 202 standards
• Self-contained: No external memory required
• SHA-3/Keccak cryptographic hashing functions provides intelligent buffer management option to receive new data in input buffer while processing existing data
• Hashing function selection among SHA3-224, SHA3-256, SHA3-384 and SHA3-512

AES core implements the Rijndael algorithm for encryption and decryption of plain text using cipher keys. It is compliant with FIPS 197 standards. The core works with a pre-expanded key, or with optional key expansion logic. The encryption core accepts new plain text every 11 clocks. The decryption core accepts new cipher text after 22 clocks when using the new key and after 11 clocks when using a pre-expanded key 

• Fully synchronous design
• Supports key sizes of 128 and 256 bits
• Supports AES-128 and AES-256 in Electronic Codebook (ECB) mode
• Other modes such as CBC, CFB, OFB, and CTR can be added as needed
• Fast core accepting data every clock is also available as per requirement

Reed Solomon IP core codec is based on IEEE 802.3bj Clause 91 specification. The cyclic code used is RS (528,514) for 7 symbol error correction and RS (544,514) for 15 symbol error correction. Encoder and Decoder are separate synthesizable cores. Different architectures are available to meet area and throughput requirements. RS-based IP cores are available for applications beyond IEEE 802.3bj.

• Flow-through design with low latency 
• RS (544,514) and RS (528,514) can be switched dynamically i.e., code word by code word
• Parallel interface for processing multiple symbols in a clock
• Ability to bypass error correction to reduce latency through the core
• Small FIFO inside the core to store the code word while it is being decoded
• No memory required

Data-backup can push your costs up by 200%, and even there are high chances of data loss. Manage erasures and optimize your data recovery costs with an IP based on Reed-Solomon codes. Data erasure is a powerful way to tighten data security. Modern applications built for data centers and the cloud can make your organization vulnerable as storage devices have a high probability of being corrupted. While data-backup solutions are useful, they can push the costs up exuberantly. Why not get a smart solution that ensures 100% data recovery in case of up to certain storage device failures? 

• Designed to improve IT asset management, it offers ready-to-use implementation with the following valuable capabilities:
• Parallel read of symbols a single clock across storage devices and fix erasures
• Provides maximum correction capability by adapting the algorithm to correct only the erasures
• Flow-through design with low latency
• Zero additional memory for encoder design 

The Ethernet controller is compliant with IEEE802.3 and it provides an interface between the host subsystem and the Media Independent Interface (MII). The 10/100 Ethernet MAC consists of DMA (TX DMA, RX DMA), TLI (TX buffer, RX buffer), 10/100 Ethernet controller. The DMA automates data transfers and frees the CPU from this task. The Transaction Layer Interface (TLI) is a 64-bit wide block designed to provide a bridge between the DMA controller and a 10/100 Ethernet controller. The TLI uses 4 Kbytes FIFO for transmit (TX Buffer) and 2 Kbytes FIFO for receive (RX Buffer)