Design Verification Engineer
Requirements
- Develop verification testbench components for chip/module level using System Verilog, C/C++.
- Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
- Define and execute detailed verification plan from spec working with architects, designers, system engineers.
- Write tests, Debug tests, automate regression scripts and regression environment.
- Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
- Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
- Excellent debugging skills in both SW and ASIC hardware.
- Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
- Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
- Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
- Good understanding of latest formal verification techniques, assertions, properties is a plus.
- Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus.
- Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus.
- Good written and oral communication skills. Ability to clearly document plans.
- ability to interface with different teams and prioritize work based on project needs.
Job Specifications
Job Category: On-Site
Job Type: Full Time
Job Function: Silicon Engineering Services
Qualification: B. Tech / M. Tech (ECE)
Years of Experience: 5-12 Yrs.