MosChip®

SEMICONDUCTOR
DESIGN SOLUTIONS

With experts catalyzing the industry for 2+ decades

Specifications to GDSII with our Semiconductor Design Solutions

25 years of revolution in silicon engineering and product engineering solutions from India to the world.

The semiconductor industry continues to lead technological advancements, driving progress across various sectors such as consumer electronics, automotive, telecommunications, and healthcare. The growing demand for more powerful, efficient, and compact devices has intensified the need for sophisticated semiconductor design and manufacturing. MosChip offers end-to-end semiconductor design solutions with a focus on cutting-edge designs tailored to the various industrial requirements. Our commitment to innovation and quality development has positioned us as leaders in the field. Our capabilities encompass every aspect of semiconductor design, from conceptualization to final product delivery, ensuring a holistic and accountable approach.

With a focus on high-performance and robust semiconductor design, MosChip leverages its extensive experience along with latest tools/technologies and proven methodologies to deliver high-quality and reliable solutions. We are dedicated to empowering our client projects with precision and excellence through our comprehensive semiconductor design solutions involving RTL design, verification, physical design, analog design and analog layout.

Key Solutions

RTL Design & Verification

With over 25 years in the industry, MosChip excels in RTL Design and Design Verification, offering in-house IP verification, low power intent verification, ASIC Prototyping, and post-silicon validation. Their expertise in SoC verification languages, peripheral system deployment, and industry-standard methodologies ensures error-free designs and reduced time-to-market. MosChip has proven invaluable to semiconductor product companies worldwide, providing custom IP verification for various standard interfaces.

Offerings

  • RTL Design & Integration
  • Micro-architecture design
  • Synthesis & Optimization
  • Low power and GLS
  • IP/VIP Development
  • Third party IP/VIP & SoC integration
  • SV/UVM Expertise
  • Assertion-based verification
  • Constrained Random & Coverage-driven verification
  • Dynamic & Static Verification
  • Metric driver verification
  • IP/SoC level verification
  • IP to SoC Verification Sign-off
  • Test bench development
  • Development of BFMs, Monitors and checkers
  • Functional and code coverage analysis
  • Verification IP development
  • Low Power Verification & CPF/UPF Flows
  • Concept to Deployment
  • IP to SoC Design & Prototyping
  • Architecture, Coding, Testing, Release & Support
  • Functional Verification

Tools & Technology expertise

USB3.0/2.0  |  PCI Express Gen5  |  Wi-Fi  |  Ethernet  |  DDR5/4  |  eMMC  |  SATA  |  HDMI  |  MIPI CSI2  |  MIPI-DSI  |  Display Port  |  CAN  |  SPI  |  UART  |  I2C  |  Interlaken  |  AMBA protocols – AXI4/5  |  AHB and APB
SystemVerilog  |  C  |  UVM  |  eRM  |  OVM  |  VMM
Python  |  Perl  |  .SH
Siemens QuestaSim  |  Cadence Xceliun  |  Synopsys VCS  |  Jasper  |  Questa Formal  |  Simvision  |  Visualizer  |  Codelink Verdi  |  Formality  |  FormalPro  |  QuestaSLEC  |  Conformal  |  VCS_LP, VCS_NLP  |  vManager
Intel/Altera  |  Cadence  |  Xilinx/AMD  |  Lattice SensAI

Physical Design & DFD Solutions

MosChip specializes in RTL to GDSII using both Cadence and Synopsys flows. We not only maintain leading EDA infrastructure for physical design, but also employ a team with dedicated subject matter experts with rich experience in the physical design flow and methodologies critical to achieving optimum performance, power, and area (PPA). Our proven flows and methodologies ensure that the design gets through the range of foundry-specific DRCs, LVS, and ERCs precisely to avoid multiple iterations avoid delays, and stay on schedule.

Offerings

  • Block-Level Place & route
  • Timing Closure & Static Timing Analysis
  • Multiple Domain Clock-Tree Synthesis
  • Physical Verification (DRC/ERC/LVS)
  • EM-IR Drop Analysis, SI Closure
  • Chip-Integration
  • Logic Synthesis & Physical Synthesis
  • Low Power Expertise – Clock Gating, Multi-Vt, Voltage Islands, Power Gating
  • O-ring design
  • Customer Designed Bump/RDL integration to chip level
  • RDL Design and Routing
  • Metal Stack selection for customers
  • Bumps and Package

Tools & Technology expertise

Cadence  |  Siemens  |  Synopsys  |  Mentor Graphics
TSMC  |  UMC  |  Global Foundry  |  IBM  |  Tower Jazz  |  and Samsung

Analog Design Solutions

Analog design solutions deal with designing and optimizing analog circuits and systems that are essential for converting real-world signals into digital data that semiconductors can process. At MosChip, we offer analog design solutions involving Analog/RF circuit design, component selection, mixed signal IP design, complex IP porting like SerDes and DDR.

Offerings

  • Complex IP porting (SerDes, DDR)
  • Long range SerDes PHY
  • Short range SerDes PHY
  • AFE for 1000Base-T PHY
  • PAM4 Transceiver Technology building blocks

Tools & Technology expertise

  • Cadence Virtuoso for schematic entry
  • Cadence Spectre for Spice Simulations
  • Cadence APS for Fast Simulations
  • Cadence Voltus for EMIR Analysis
  • Cadence Xcelium for Digital and AMS Simulations
  • Cadence Virtuoso for layout
  • Cadence Pegasus for LVS
  • Mentor Calibre for LVS and DRC
  • MATLAB for architecture Simulations
  • Verilog A for Circuit modelling
  • System Verilog for wreal modelling
  • SOS for version Control
TSMC  |  Samsung  |  Intel  |  Global foundries

Analog Layout Solutions

Over the past two decades, MosChip has accumulated extensive experience in the development of layouts for a diverse range of analog and mixed-signal chips. MosChip's involvement has been confined to the meticulous planning and implementation of tape-outs specifically tailored for the 14nm, 10nm, and 7nm process nodes. This proficiency is underscored by our collaborations with leading foundries such as TSMC, GlobalFoundries, and Samsung. We have expertise in managing layouts for high-frequency PLLs, and in SerDes, PMUs, RF designs, Memories, Data Converters, and DDR and GDDR IOs.

Offerings

  • High Speed SerDes up to 112Gbps
  • Power Management Layouts – LDO, BGR, SMPS, Bias blocks, Buck Boost converters, etc.
  • I/O cells – GPIOs, LVDS, DDR IOs and GDDR IOs
  • Data Converters – ADC, DAC with different architectures (Pipeline, SAR ADC, Flash ADC, Current steering DAC and R-2R ladder DAC)
  • RF Layouts – LNA, Mixers, RF transreceiver
  • Memory Layouts – Register files, Dense RAM, Cache Memory, CAM Memory
  • Clock Generators – Phase Locked Loop, Delay Locked Loop

Tools & Technology expertise

  • TSMC – – N2  |  N3E  |  N3P  |  5FF  |  6FF  |  7FF  |  12FF  |  16FF
  • TSMC – 22nm  |  28nm  |  130nm | 180nm
  • SAMSUNG – 2nm | 3nm  |  4nm  |  5nm  |  7nm
  • GF – 12nm  |  14nm  |  22nm  |  40nm  |  55nm  |  65nm

Success Stories

Success Story

Pre/Post Silicon Validation

The Client is US based leading semiconductor company having expertise in…

Success Story

UVM based Verification for FPGA

The Client is US based leading semiconductor company having expertise in…

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