Product design and DFT

Good Practice in Design for Test (DFT) methodology during any SoC design & verification can enhance time to market plus reduce manufacturing costs. MosChip’s delivers testable silicon along with optimal test time. We have enabled 200+ tapeouts, 40nm TSMCLP Design, 28nm TSMCLP, verification (Testchip), 55mn gate density largest design and silicon turn-on across with 99% of coverage.

With a proven, methodologies and physical flow design, along with dedicated experts, MosChip have helped many clients with successful tapeouts. We are among few the first companies to tapeout multiple SoC’s.

Key Differentiators:

  • Unique combination of silicon & systems
  • 16+ years of product development experience
  • Outstanding process, templates, structures & checklist for scaling up
  • Robust Internal Design flows
  • In-house developed reusable cores (USB2.0 & 3.0)
  • Early adopters of advanced ASIC Verification methodologies like VMM, OVM & UVM
  • Developed scalable, configurable & reusable verification test bench
  • Large design exposure
  • Analog/Mixed Signal Expertise
  • Power Optimization Experience
  • Yield enhancement services

SoC & ASIC Expertise

  • Standards & system level understanding
  • System architecture, FPGA design, pre-& post silicon validations
  • ASIC design, integration, verification, synthesis, design closure, power & package analysis
  • Synopsys, Cadence, Magma flow
  • ARM9 & ARM Cortex based SoCs
  • General Purpose, Storage & Network SoC’s
  • Multi-Processor Cores
  • Video, Graphics & Processor sub-systems