ASIC Verification IP’s

MosChip’s ASIC Verification IP’s are reusable verification modules that consist of bus functional models, traffic generators, protocol monitors, and functional coverage blocks. MosChip’s plug-and-play Verification IP’s cut down the overall verification time for the companies and enables the companies to quickly market their product.

Our list of ASIC Verification IP’s is:

IP Name Details
USB2.0 Device verification IP – UTMI Interface

 

USB2.0 Device BFM is a Verilog behavioral model, which is a USB2.0 compliant and supports high speed, full speed & low speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a parallel UTMI interface.
USB2.0 Host verification IP – Serial Interface

 

USB Host BFM is a Verilog behavioral model, which is a USB2.0 compliant and supports high speed, full speed & low speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface
USB1.1 verification IP for USB1.1 HUB as a DUT – Serial Interface

 

This setup consists of integrated upstream Host with Four port HUB (DUT) downstream Devices of Full speed & Low speed, with strength modeling on Upstream Host port & Downstream Device ports for the emulation of the Host & Device dynamic attach & detach logic, It supports control, bulk, interrupt & isochronous transfers
USB1.1 Host verification IP – Serial Interface

 

USB host BFM is a Verilog behavioral model, which is a USB1.1 compliant and supports full & low speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface
Ethernet 10/100 verification IP

 

This BFM is a Verilog behavioral model, which is IEEE802.3 compliant and supports the 10/100 half/full duplex modes of operations. It is capable of generating all types of packets and injects various error conditions
HDMI 1.1 TX verification IP

 

This BFM is Verilog behavioral model, which is complaint of HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings
HDMI TX host application model

 

This BFM is Verilog behavioral model, which is complaint of HDMI 1.1 specification. This BFM generates the video data, audio data, and auxiliary info-frames and transmits on the TX lines
USB2.0 HUB verification IP – UTMI Interface

 

USB2.0 HUB BFM is a Verilog behavioral model, which is a USB2.0 compliant and supports high speed full speed & low speed USB transactions. It supports control, bulk, interrupt, isochronous and Split transactions, which works on a parallel UTMI interface.
USB3.0 device verification IP – (Under development)

 

The OVM compliant USB3.0 device OVC supports USB3.0 Device functionality. It consists of OVM verification capabilities like sequencer, checker and coverage metrics. The main functions of the USB3.0 device OVC is to perform USB3.0 device link training, link Initialization, link recovery, device enumeration, device data transfers with link flow control, and power management operations, packet formation/decoding is done by the device protocol layer and framing/de-framing is done by the device link layer.
OTG verification IP – UTMI Interface

 

USB2.0 OTG BFM is a Verilog behavioral model, which is a USB2.0 compliant and supports high speed & full speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on parallel UTMI interface
Parallel Port verification IP

 

This model implements the functionality of SPP, Nibble, Byte, ECP, ECP RLE, EPP modes and supports the faster data rates up to 2Mbytes/s. This IP sends and receives data based on the configuration settings using parallel port registers and stores the data for the integrity checks.
IrDA (SIR/MIR/FIR/VFIR) verification IP

 

This BFM is a Verilog behavioral model, which can operate in 4 different encoding/decoding modes of SIR/MIR/FIR/VFIR and so it has division between them in its structure. The SIR encoding/decoding operates by using a standard UART as its controller.
SATA Device application model

 

This BFM is a Verilog behavioral model, emulates the functionality of the device application model. The main functions of this model are to initialize SATA Device DUT, decode the commands and generate appropriate response to the DUT   and storing the data for integrity checks
SATA Host application model

 

This BFM is a Verilog behavioral model, emulates the functionality of the host application model. The main functions of this model are to initialize SATA Host DUT, create command and data structures, initiating the DUT, storing the data for integrity checks.
IrDA host application model

 

This BFM is a Verilog behavioral model, which can generate SIR/MIR/FIR/VFIR frames to USB1.1 host model and checks for the functional issues while receiving the IrDA frames from USB host model. In transmit mode, IrDA host application model prepares the IrDA frames based on mode selection and send to USB1.1 host verification IP, USB1.1 host interface model prepares the USB packets based on the IrDA frames and send to DUT
SATA Device Verification IP

 

This BFM is a Verilog behavioral model, emulates the link, transport and application layers of SATA protocol. It supports PIO/DMA/FPDMA/QDMA modes and generates all the functional scenarios which includes power management, flow control mechanism etc.  It can inject/detect error scenarios and captures the data for integrity checks. It receives the commands from the SATA host controller DUT and responds accordingly.

 

SATA Host Verification IP

 

This BFM is a Verilog behavioral model, emulates the functionality of the host based on link, transport and application layers of SATA protocol. It supports PIO/DMA/FPDMA/QDMA modes and generates all the functional scenarios which includes power management, flow control mechanism etc.  It is able to inject/detect error scenarios and captures the data for integrity checks. This can generate/checks the stimulus for the SATA Device controller as a DUT.

 

PCI verification IP

 

PCIe model purchased from nSYS. This can be configured either PCIe Root complex or end point mode. This model comprises of PCIe checkers and monitors, which checks the traffic flow and protocol violations
I2C verification IP

 

Inter-Integrated-Circuit serial interface for connecting peripherals. Supports 100 Kbps-Standard mode, 400Kbps-Fast mode, 3.4 Mbps-High speed mode and 5 Mbps-Ultra-fast-mode. If any of the modes are not supported. Current IP supports Master and Slave both.
HDMI 1.1 RX verification IP

 

This BFM is Verilog behavioral model, which is complaint of HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
Serial port verification IP

 

This model implements RS-232 asynchronous transmit and receive logic. This model supports the baud rates from 50bps to 6mbps. This IP can be configurable for data width (5,6,7, and 8), stop bits (1 or 2) and parity (None, Even, Odd, mark, space).