ASIC Design IP’s

MosChip has more than 30+ IP designs in its portfolio. We provide design verification IP’s and validation services ranging from analog, mixed-signal, ASIC, SoC, digital logic and custom IP. We use advanced verification methods for projects as per client’s process.

Our Design IP’s are:

IP Name


USB2.0 Host controller The USB 2.0 Host Controller implements an EHCI interface and OHCI interface that interfaces UTMI USB port transceiver on one side and to an application device core / system’s microprocessor on the other side using VCI interface. The EHCI controller is used for all high-speed communications to high-speed-mode devices connected to the root port.
USB2.0 Device controller USB 2.0 Device controller implements a complete high/full speed peripheral controller that interfaces UTMI USB port transceiver on one side and to an application device core / system’s microprocessor on the other. It supports control, bulk, interrupt and isochronous transfers defined by USB2.0 specifications.
USB2.0 OTG controller On-The-Go Controller (OTG) is USB2.0 OTG supplement compliant with support of high-, full-, and low-speed operation. It supports UTMI interface to connect to an USB OTG PHY. It uses VCI bus to interface with an application device core / system’s microprocessor external processor.


UTMI+ to ULPI wrapper The UTMI+ (USB Transceiver Macrocell Interface Plus) to ULPI (UTMI+ Low power Interface) wrapper takes care of the ULPI register interaction with the USB 2.0 PHY. Converts 32 bit data interface on UTMI+ interface onto 8 bit data interface defined by ULPI specifications and vice versa. On power on reset takes care of the PHY initialization.
USB 1.1 device controller USB device controller (UDC) works like a source and destination of data for the USB host controller.  USB device protocol is implemented in this controller. This controller will respond to all standard commands specified in the USB1.1 specification. This is compliant with USB1.1 specification.  Have the clock recovery mechanism to recover the clock from the data on dp and dm lines and 48MHz external clock.


SATA II v2.6 Host Controller The SATA II Host Controller implements an AHCI/Emulation interfaces that interfaces with SATA PHY using SAPIS interface on one side and to an application on the other side using VCI interface. Emulation interface is used to backward compatible with existing software and supports both PIO and DMA modes of operation. AHCI is Advanced Host Controller Interface, which is a hardware mechanism that allows software to communicate with Serial ATA devices. It supports PIO, DMA and FPDMA modes of operation and also supports NCQ using FPDMA mode. It has aggressive power management capabilities.
SATA II v2.6 Device Controller The SATA II Device Controller interfaces with SATA PHY using SAPIS interface on one side and to an application on the other side using VCI interface. It supports PIO, DMA, QDMA, FPDMA modes of operation and also supports NCQ using FPDMA mode of operation. It also supports SATA power management features.


Storage Security: IEEE P1619 compliant XTS-AES XTS-AES implements the standard AES cipher in the XTS mode for encryption and decryption of Data at rest. It has two implementations, one implementation can handle the throughputs of SATA and other implementation can handle throughput of Flash. It has supports for both 256 and 512 bit key widths
Ethernet 10/100 MAC Ethernet controller is compliant to IEEE802.3 and it provides interface between the host subsystem and the Media Independent Interface (MII). The 10/100 Ethernet MAC consists of DMA (TX DMA, RX DMA), TLI (TX buffer, RX buffer), 10/100 Ethernet controller. The DMA automates data transfers and frees the CPU from this task. The Transaction Layer Interface (TLI) is a 64-bit wide block designed to provide a bridge between the DMA controller and a 10/100 Ethernet controller. The TLI uses 4 Kbytes FIFO for transmit (TX Buffer) and 2 Kbytes FIFO for receive (RX Buffer).


TCP/IP off load engines 10/100 TCP/IP off load engine is a stateless TOE engine. Amongst other features it has TCP segmentation offload (TSO) in which TCP layers passes a very large segment through the stack to the TOE HW, which segments i\t into several packets. This method improves performance by reducing per packet software overheads within the network stack. The segmentation is performed inside HW. Other important offloads handled by the TOE block are TCP,UDP and IP checksum calculation and verification. With TOE engine programmed TCP/IP software stack need not calculate and update checksum fields in the protocol headers.
HDMI 1.1 Transmit controller HDMI Transmitter is a compact audio/video interface for transmitting uncompressed digital data. It takes 24 bit video data and SPDIF/I2S audio data from respective sources and sends it over HDMI interface. It has provided a I2C interface used to read capabilities of a SINK. It has HDCP engine to encrypt video/audio data being transmitted.
HDMI 1.1 Receive controller HDMI Receiver is a compact audio/video interface for receiving uncompressed digital data. It receives 30 bit video and audio data along with control information interleaved into HDMI packets on 3 HDMI channels and sends it over video (RGB interface) and audio (SPDIF/I2S interface). It has HDCP engine to decrypt video/audio data being received. It has a I2C channel to provide receiver capabilities information to the transmitter.
PCI v2.1 Master/Slave controller The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3. It has fully customizable PCI Configuration Space. The controller supports both 32 and 64 bit PCI bus path. The application interface can be configured of 32 bit as well as 64-bit interface as per requirements. The IP supports both master and slave operations and PCI power management.
PCI v2.1 Host Controller The PCI Host controller offers PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1. PCI Host Bridge contains internal arbiter to manage up to 4 external devices.
ISA bus interface controller The ISA (Industry standard architecture) local bus controller is used to expand the serial ports and parallel ports using external ISA based chips. This controller operates at 3-bit address line, 8-bit data bus with some control signals.

Supports both Intel (16 mode) or Motorola (68 mode) data bus Interface.

Cascade (Proprietary) peripheral expansion bus controller Cascade bus is a 13-pin bidirectional bus controller used to connect two chips. Chip that is connected to system is primary and the chip that is extended using cascade bus is a secondary. These two chips works like a master/slave. For accessing the registers of secondary chip, cascade logic on the primary works like a master and secondary chip cascade logic works as a slave. For DMA and interrupt transfers secondary chip works like a master and primary chip works like a slave.


DMA Controller The memory 2 memory DMA controller transfers data from memory location to other memory location. DMA operation begins when software enables a DMA, after setting the source and destination starting addresses, transfer count, and control information. The DMA engine moves the data block and the DMA operation ends naturally when the number of bytes specified by the transfer count has been moved.


I2C Master Controller The I2C (Inter Integrated Circuit) master controller operates using two wires – SCL and SDA. The controller supports programmable speeds up to 400 KHz. It has a generic application interface for integration.


SPI Master Controller The SPI (Serial Peripheral Interface) host controller supports maximum 4 devices and has programmable SPI clock. This supports full duplex synchronous data transfers. The controller supports variable length of transfer word up to 32 bits and supports programmable SPI Clock Polarity and Phases.
UART/Serial Port – RS232, RS422, RS485 The Serial Port IP is Single Port Standalone IP, which supports all the features in the modes like 16C450, 16C550, 16C550Ex, 16C650, 16C750/16C950. Supports bi-directional speeds from 50 bps to 16 Mbps per serial port. Supports full serial modem control. Supports Hardware as well as Software flow control.


IrDA controller – SIR, MIR, FIR The IRDA controller supports data rates from 2.4 Kbps to 115.2Kbps in SIR mode, 1.152 Mbps in MIR (Medium IR) and 4Mbps in FIR mode.


IEEE1284 Parallel Port controller The IEEE1284 compliant parallel port controller supports faster data rates up to 2.0Mbytes/sec. Supports Nibble mode, Byte Mode, EPP, ECP. Auto-negotiation is implemented in hardware.


Generic GPIO controller General Purpose I/O pins are used for system control and connection of various devices. This (GPIO) controller provides dedicated general-purpose pins that can be configured as either inputs or outputs. There can be 32 (programmable*) General Purpose Input/Output pins. All the GPIO pins in input mode can generate interrupt. Each GPIO can be configured independent of all other GPIO. The GPIO’s allow data input and IRQ generation.


I2S audio interface controller The I2S-bus (Inter-IC) sound bus is a serial link for transmitting stereo audio between devices in systems. The I2S interface core allows to stream audio to and from I2S capable devices. The I2S interface consists of two separate cores, a transmitter and a receiver. Both operate in master mode.


Random number generator The random number generator f\generates true random numbers using a LFSR. The LFSR can only be read by the internal CPU.


AHB to VCI Bus Bridge VCI to AHB bus bridge controller is a protocol converter which accepts the transaction from VCI master and converts into equivalent AHB transactions. This bridge accepts all valid VCI byte enables and VCI transaction can be any length. VCI I/F is a 64-bit interface, AHB I/F is 32 or 64 bit interface it is a programmable option.


Synchronous Single AHB64 to Multi AHB64 converter This converts 64 bit AHB transactions into multi 64 bit transactions.


Synchronous Single AHB32 to Multi AHB32 converter This converts single 32 bit AHB transaction into multi 32 bit AHB transactions.


USB3.0 Host Controller (under development) USB3.0 Host controller IP is compliant to xHCI specifications 0.96 and capable of supporting Super Speed, High Speed, Full Speed and Low Speed devices. The Host Controller IP supports parallel operation of Super Speed and USB2.0 on Root Hub Ports. Host controller supports all USB3.0 and USB2.0 Link Power Management features. The Host Controller IP provides simple VCI interface to connect to any System Bus.