Physical Design Engineer
Qualification: Bachelors or Masters (Computer/Electronics Engineering)
Experience: 2-5 Yrs
Responsible for SCAN, MBIST, JTAG, Vector generation and Verification and ATE post-silicon debug for complex 28nm and 22nm SoC.
1) Experience in Scan insertion & Compression, Pattern Generation and Validation.
2) Expereince in Boundary scan, LBIST, MBIST, JTAG and Low Power DFT atChip level and IP level
3)Tools: Fastscan/ TestKompress /DFTCompiler/ DFTMax/ DFTAdvisor/ TetraMax.
1) In depth knowledge and hands on experience in scan insertion, MBIST insertion and Memory Validation, ATPG, coverage analysis, Transition delay test coverage analysis.
2) Understand ATPG failures, debug or resolve DRC issues, Chain trace issues, Debug and Fix gate level Pattern simulation issues, both No-Timing and Timing simulation.
3) Knowledge of IDDQ constraints generation and validation and silicon bring up and debug.
4) Expertise in scripting languages like PERL,Shell etc.