Verification IPs
Reduce Trunaround time & Faster SoC Design Verification
Verification IPs
MosChip’s verification IP’s reusable verification modules that consist of USB functional modules, traffic generators, protocol monitors, and functional coverage blocks. MosChip’s verification helps you accelerate the development of the verification process. MosChip has more than 30+ verification IPs. Our verification IP’s fit into every verification environment and support all simulators’ verification languages.
Interface IPs
- USB2.0 Device Verification IP - UTMI Interface
- USB2.0 Host Verification IP - Serial Interface
- USB1.1 Verification IP for USB1.1 HUB as a DUT – Serial Interface
- USB1.1 Host Verification IP - Serial Interface
- USB2.0 HUB Verification IP - UTMI Interface
- USB3.0 Device Verification IP (Coming Soon)
- PCI verification IP
- Ship your products with best in class USB IP design
- SHA1 64/128 Crypto Core
- Advanced Encryption Standard Core (AES)
- Reed Solomon FEC Codec
- Reinforce Data Security with our Erasure IP
- SHA-3 Secure Hash Function Core
- xSPI Verification IP
- USB Device Controller
- USB Host Controller
- USB Dual Role Device (DRD) Controller
- USB ReTimer
USB2.0 Device BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which work on a parallel UTMI interface.
USB Host BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
This setup consists of an integrated upstream Host with Four-port HUB (DUT) downstream Devices of Full speed & Low speed, with strength modeling on Upstream Host port & Downstream Device ports for the emulation of the Host & Device dynamic attach & detach logic, It supports control, bulk, interrupt & isochronous transfers.
USB host BFM is a Verilog behavioral model, which is USB1.1 compliant and supports full & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
USB2.0 HUB BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high-speed full speed & low-speed USB transactions. It supports control, bulk, interrupt, isochronous and Split transactions, which works on a parallel UTMI interface.
The OVM compliant USB3.0 device OVC supports USB3.0 Device functionality. It consists of OVM verification capabilities like a sequencer, checker, and coverage metrics. The main functions of the USB3.0 device OVC are to perform USB3.0 device link training, link Initialization, link recovery, device enumeration, device data transfers with link flow control, and power management operations, packet formation/decoding is done by the device protocol layer and framing/de-framing is done by the device link layer.
PCIe model purchased from nSYS. This can be configured in either PCIe Root complex or endpoint mode. This model comprises PCIe checkers and monitors, which check the traffic flow and protocol violations.
MoscHIP SuperSpeed USB IP solution based on the USB 3.2 Gen 2 specification
The comprehensive SuperSpeed USB IP offering consists of the device, host, drd controllers, and retimer with and without support for the USB Type-C. Compatible with USB3.2 Gen 2×2, USB 3.1 and USB 3.0. Enabling quick development of advanced chip designs, incorporating the 5.0 Gbps SuperSpeed USB standard.
- Lower the engineering effort with USB IP Subsystem, PHY, and Controller
- Decreases BOM costs with integrated features
- Availability of standard drivers that are compatible with open sources
SHA-1 IP core implements Secure Hash Algorithms specified in FIPS 180-4 standard. Common cores are available for ASIC and FPGA applications.
Fully synchronous design
MosChip core supports higher frequency and accepts data every 41 or 21 clocks as opposed to every 80 clocks for IP’s available in the market.
- SHA1 supports SHA1 as per FIPS 180-4
- 64-bit or 128-bit data path interface
- Padding is added as per the specification to make message a multiple of 512-bit block
- SHA1 produces message digest of 160 bits
- Accepts new block every 41 clocks (64-bit data path) or 21 clocks (128-bit data path)
MosChip AES core implements Rijndael algorithm for encryption and decryption of plain text using cipher keys. It is compliant with FIPS 197 standard.
Fully synchronous design
The core works with a pre-expanded key, or with optional key expansion logic. Encryption core accepts new plain text every 11 clocks. Decryption core accepts new cipher text after 22 clocks when using new key and after 11 clocks when using pre-expanded key.
- Supports key sizes of 128 and 256 bits
- Supports AES-128 and AES-256 in Electronic Codebook (ECB) mode
- Other modes such as CBC, CFB, OFB and CTR can be added as needed
- Fast core accepting data every clock is also available as per requirement
MosChip Reed Solomon IP core codec is based on IEEE 802.3bj Clause 91 specification. Cyclic code used is RS (528,514) for 7 symbol error correction and RS (544,514) for 15 symbol error correction. Encoder and Decoder are separate synthesizable cores.
Flow-through design with low latency
Different architectures available to meet area and throughput requirements. RS based IP cores available for applications beyond IEEE 802.3bj.
- RS (544,514) and RS (528,514) can be switched dynamically i.e. code word by code word
- Parallel interface for processing multiple symbols in a clock
- Ability to bypass error correction to reduce latency through the core
- Small FIFO inside the core to store the code word while it is being decoded
- No memory required
Data-backup can push your costs up by 200%, and even there are high chances of data loss. Manage erasures and optimize your data recovery costs with an IP based on Reed-Solomon codes.
Data erasure is a powerful way to tighten data security
Modern applications built for data centers and the cloud can make you organization vulnerable as storage devices have a high probability of being corrupted. While data-backup solutions are useful, they can push the costs up by more than 200%. Why not get a smart solution that ensures 100% data recovery in case of up to certain storage device failure?
Designed to improve IT asset management, it offers ready-to-use implementation with following valuable capabilities:
- Parallel read of symbols a single clock across storage devices and fix erasures
- Provides maximum correction capability by adapting the algorithm to correct only the erasures
- Flow-through design with low latency
- Zero additional memory for encoder design
MosChip SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach. The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard. A common core is available for diverse ASIC & FPGA applications.
Compliant with NIST’s FIPS 202 standards
The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications, including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.
- Self-contained: No external memory required
- SHA-3/Keccak cryptographic hashing functions provides intelligent buffer management option to receive new data in input buffer while processing existing data
- Hashing function selection among SHA3-224, SHA3-256, SHA3-384 and SHA3-512
MosChip xSPI Verification IP provides verification of xSPI (Extended SPI) for devices using the Serial Parallel Interface (SPI) protocol for master and slave modes. It is a reusable, configurable, pre-verified, and plug-and-play verification component developed in System Verilog.
JESD216 protocol with multi-thread logic
MosChip xSPI VIP supports a comprehensive set of protocol, methodology, verification features to help accelerated verification closure of SPI Bus and Flash-based designs. It can be seamlessly integrated with the protocol-aware debug environment to provide operations, transactions, and memory content view for fast and efficient debug.
- JESD 251 compliant Protocols 1 & 2
- Support flexible erase options (4/8/32/64KB block erase)
- Flexibility – Single VIP supports multiple SPI protocols
- Plug-and-play integration with most SoCs
- Allows backdoor read/write access to Mode Registers and Device Memory
- Dynamic modification of timing parameters
This USB Device softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Device implementations along with backward compatibility to High/Full speed modes with Type-C or standard USB-Device connector.
USB Device Controller with protocol-layer & link-layers implementation
USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full Speed modes. Support PIPE and UTMI+/ULPI interfaces with full link power management
- AMBA-AXI system-bus interface for configuration-space access and data-path interface with Inbuilt DMA engines that provide enhanced data transfer capability
- Up to 16 IN and OUT Endpoints including control Endpoint
- Parameterized design allows configuration of internal buffers based on application needs
- Clock domain crossing mechanism between USB and XDC/system-bus logic provides flexibility for easy integration
This eXtensible Host Controller Interface (xHCI) compliant USB-Host softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-host implementations along with backward compatibility to High/Full/Low speed modes with Type-C or standard USB-host connector.
eXtensible Host Controller Interface with USB3.2 x2 link protocol
USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes. Support PIPE and UTMI+/ULPI interfaces with full link power management. Clock domain crossing mechanism between USB and xHCI/system-bus logic provides flexibility for easy integration.
- AMBA-AXI system-bus interface for configuration-space access and data-path interface
- Bulk-stream for USB Attached SCSI Protocol (UASP) transfers
- Up to 16 IN and OUT Endpoints including control Endpoint
- Sideband interrupt and message signal interrupts
- Precision Time Measurement (PTM)
This Dual Role Device (DRD) softcore semiconductor IP is designed for applications requiring both USB Host and Device implementation. This core comprises USB3.2 SSP, SS, HS/FS/LS Host and Device controllers in a single codebase that supports role-swap functionality.
Parameterized design
eXtensible Host Controller Interface with USB protocol-layer, and link-layers implementation. USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes
- Support PIPE and UTMI+/ULPI interfaces with full link power management
- AMBA-AXI system-bus interface for configuration-space access and data-path interface
- Up to 16 IN and OUT Endpoints including control Endpoint
- Parameterized design allows configuration of internal buffers based on application needs
- Clock domain crossing mechanism between USB and system-bus logic provides flexibility for easy integration
This ReTimer Controller softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Retimer implementations. The core is optimized for low power requirements.
The core is highly power efficient for port or cable retimer applications
Softnautics USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations. The IP has been verified in simulation and is synthesis clean for FPGA implementations.
- SuperSpeedPlus @10Gbps with fallback to SuperSpeed @5Gbps
- USB-Link parallel data-path 20bit for SS, and 32bit for SSP
- Implements Digital-PHY PCS as part of the core supporting 8b/10b and 128b/132b codec with scrambler and descrambler, error detection-correction, Clock offset compensation with elasticity buffer, LFPS, full LPM, and compliance-mode
- Easy customization for interface to PMA/SERDES logic and sideband signaling
USB2.0 Device BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which work on a parallel UTMI interface.
USB Host BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high speed, full speed & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
This setup consists of an integrated upstream Host with Four-port HUB (DUT) downstream Devices of Full speed & Low speed, with strength modeling on Upstream Host port & Downstream Device ports for the emulation of the Host & Device dynamic attach & detach logic, It supports control, bulk, interrupt & isochronous transfers.
USB host BFM is a Verilog behavioral model, which is USB1.1 compliant and supports full & low-speed USB transactions. It supports control, bulk, interrupt & isochronous transfers, which works on a serial DP/DM interface.
USB2.0 HUB BFM is a Verilog behavioral model, which is USB2.0 compliant and supports high-speed full speed & low-speed USB transactions. It supports control, bulk, interrupt, isochronous and Split transactions, which works on a parallel UTMI interface.
The OVM compliant USB3.0 device OVC supports USB3.0 Device functionality. It consists of OVM verification capabilities like a sequencer, checker, and coverage metrics. The main functions of the USB3.0 device OVC are to perform USB3.0 device link training, link Initialization, link recovery, device enumeration, device data transfers with link flow control, and power management operations, packet formation/decoding is done by the device protocol layer and framing/de-framing is done by the device link layer.
PCIe model purchased from nSYS. This can be configured in either PCIe Root complex or endpoint mode. This model comprises PCIe checkers and monitors, which check the traffic flow and protocol violations.
Network IPs
Ethernet 10/100 verification IP
This BFM is a Verilog behavioural model, which is IEEE802.3 compliant and supports the 10/100 half/full duplex modes of operations. It can generate all types of packets and injects various error conditions
Communication IPs
- Parallel Port verification IP
- IrDA (SIR/MIR/FIR/VFIR) verification IP
- IrDA Host Application Model
- I2C Verification IP
- Serial Port Verification IP
This model implements the functionality of SPP, Nibble, Byte, ECP, ECP RLE, EPP modes and supports the faster data rates up to 2Mbytes/s. This IP sends and receives data based on the configuration settings using parallel port registers and stores the data for integrity checks.
This BFM is a Verilog behavioral model, which can operate in 4 different encoding/decoding modes of SIR/MIR/FIR/VFIR and so it has a division between them in its structure. The SIR encoding/decoding operates by using a standard UART as its controller.
This BFM is a Verilog behavioral model, which can generate SIR/MIR/FIR/VFIR frames to the USB1.1 host model and checks for the functional issues while receiving the IrDA frames from the USB host model. In transmit mode, the IrDA host application model prepares the IrDA frames based on the mode selection and sends them to the USB1.1 host verification IP, USB1.1 host interface model prepares the USB packets based on the IrDA frames and sends them to DUT.
Inter-Integrated-Circuit serial interface for connecting peripherals. Supports 100 Kbps-Standard mode, 400Kbps-Fast mode, 3.4 Mbps-High speed mode, and 5 Mbps-Ultra-fast-mode. If any of the modes are not supported. Current IP supports Master and Slave both.
This model implements RS-232 asynchronous transmit and receive logic. This model supports the baud rates from 50bps to 6mbps. This IP can be configurable for data width (5,6,7, and 8), stop bits (1 or 2), and parity (None, Even, Odd, mark, space).
This model implements the functionality of SPP, Nibble, Byte, ECP, ECP RLE, EPP modes and supports the faster data rates up to 2Mbytes/s. This IP sends and receives data based on the configuration settings using parallel port registers and stores the data for integrity checks.
This BFM is a Verilog behavioral model, which can operate in 4 different encoding/decoding modes of SIR/MIR/FIR/VFIR and so it has a division between them in its structure. The SIR encoding/decoding operates by using a standard UART as its controller.
This BFM is a Verilog behavioral model, which can generate SIR/MIR/FIR/VFIR frames to the USB1.1 host model and checks for the functional issues while receiving the IrDA frames from the USB host model. In transmit mode, the IrDA host application model prepares the IrDA frames based on the mode selection and sends them to the USB1.1 host verification IP, USB1.1 host interface model prepares the USB packets based on the IrDA frames and sends them to DUT.
Inter-Integrated-Circuit serial interface for connecting peripherals. Supports 100 Kbps-Standard mode, 400Kbps-Fast mode, 3.4 Mbps-High speed mode, and 5 Mbps-Ultra-fast-mode. If any of the modes are not supported. Current IP supports Master and Slave both.
This model implements RS-232 asynchronous transmit and receive logic. This model supports the baud rates from 50bps to 6mbps. This IP can be configurable for data width (5,6,7, and 8), stop bits (1 or 2), and parity (None, Even, Odd, mark, space).
Storage Interface
SATA Device application model
This BFM is a Verilog behavioural model, emulates the functionality of the device application model. The main functions of this model are to initialize SATA Device DUT, decode the commands and generate appropriate response to the DUT and storing the data for integrity checks.
SATA Host application model
This BFM is a Verilog behavioural model, emulates the functionality of the host application model. The main functions of this model are to initialize SATA Host DUT, create command and data structures, initiating the DUT, storing the data for integrity checks.
Display IP
- HDMI 1.1 RX Verification IP
- HDMI TX Host Application Model
- HDMI 1.1 TX Verification IP
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is a complaint of HDMI 1.1 specification. This BFM generates the video data, audio data, and auxiliary info-frames and transmits them on the TX lines.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.
This BFM is a Verilog behavioral model, which is a complaint of HDMI 1.1 specification. This BFM generates the video data, audio data, and auxiliary info-frames and transmits them on the TX lines.
This BFM is a Verilog behavioral model, which is the complaint of the HDMI 1.1 specification. This BFM captures the incoming video data, audio data, and auxiliary info-frames and verifies the data based on HDCP enable/disable and decryption enables settings.