Current Openings
MosChip Technologies, USA has an opening at Santa Clara for:
Physical Design Engineer Lead
Job Description
Review RTL code, synthesize design, and analyze timing, area & power reports. Develop UNIX shell, TCL & PERL scripts to automate the RTL synthesis process. Develop timing constraints file for synthesis, physical design & timing analysis tools. Physical design implementation including floor planning, power planning, placement, clock tree synthesis, routing, crosstalk analysis & timing closure for complex designs. Sign-off timing analysis, physical verification & IR drop analysis. Develop methodologies & scripts to automate the physical design process. Evaluate EDA tools for chip design flow.
Requirements
Master’s Degree or foreign equivalent in Computer Science, Computer Applications, Information Technology, or related field plus 2 years experience in the job offered ASIC Design Engineer, Manager, or related job. In the alternative will accept a Bachelor’s degree or foreign equivalent in Computer Science, Computer Applications, Information Technology, or related field plus 2 years experience in the job offered, ASIC Design Engineer, Manager, or related job. Must be able to travel temporarily to client sites & or relocate throughout the U.S.
*** This position qualifies for the Employee Referral program.