Review RTL code, synthesize design, and analyze timing, area & power reports. Develop UNIX shell, TCL & PERL scripts to automate the RTL synthesis process. Develop timing constraints file for synthesis, physical design & timing analysis tools. Physical design implementation including floor planning, power planning, placement, clock tree synthesis, routing, crosstalk analysis & timing closure for complex designs. Sign-off timing analysis, physical verification & IR drop analysis. Develop methodologies & scripts to automate the physical design process. Evaluate EDA tools for chip design flow.