Senior ASIC Verification Engineer
5 to 10 years
B.E. / B. Tech in Electronics & Communication
Worked in developing the SV/UVM environment and its components from scratch. Exposure to memory controllers like DDR4, RLDRAM, QDR is preferable. Coverage, system Verilog assertions, formal tools and serial protocol expertise is expected.
Roles & Responsibilities
- Develop block and system-level test benches and verification environments using Verilog/System Verilog, C/C++, System C, UVM/OVM/VVM and/or other verification languages as appropriate.
- Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
- Experience in ASIC/SoC verification activities and should have participated in successful completion of at least one ASIC/SoC project from Specifications to Silicon.
- Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC.
- Good understanding of ARM processor architecture is plus. Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, Low power and processor verification. Must have experience in developing BFM and functional models in Verilog/System Verilog/ UVM/OVM/VVM.
- Proven experience of the design verification methodologies such as UVM/OVM/VVM, assertion- based coverage driven verification (code & functional coverage), constraint random test generation.
- Must have experience in Make and proficient in scripting using Perl, Tcl, etc.
- Must have worked on developing verification environment and test cases
- Must have conducted functional simulations, exposure to functional coverage and bug management schemes.
- Protocol Knowledge on PCIe, USB2.0/3.0, Ethernet and LPDDR2/DDR3 is added advantage.
- Self-motivation, flexibility, with strong inter-personal skills Good communication skills, oral and written. “