Physical Design Manager

Hyderabad -Full Time


12+ years


BTech/BE in ECE or an MTech/ME in VLSI/Digital

Job Description

Experience in Physical Design including Floor planning, Placement, Clock Tree synthesis, Route, Optimization, SI analysis and Repair, STA, IR-drop analysis and DRC/LVS

Roles & Responsibilities:

  • Should have been involved in at least 20 multi-million gate chip tape outs
  • Should have worked on full chip/top level on at least 4 chips
  • Should have expertise in 14nm/10nm/7nm process nodes
  • Should have expertise in Logic/Physical Synthesis and Formal Verification
  • Should have understanding about internal scan, ATPG, BIST and JTAG
  • Should be doing hands-on work currently
  • Should be strong in TCL programming
  • Should be well versed with the Cadence or Synopsys tool set
  • Should have been managing teams at least for 2 years
  • Should have good communication and articulation skills
  • Working experience with teams sitting in different physical locations and time zones is a plus
  • Should have had a decent stay at each and every previous employer
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