ASIC RTL Design Engineer
Hyderabad, India -Full Time
B.E. / B. Tech in “Electronics” or “Electronics & Telecommunication”
Roles and Responsibilities
- Worked on ASIC projects.
- Knowledgeable of Full chip cycle.
- Good understanding of Verilog (RTL), Digital design principles, Timing Constraints
- Front End Design and Implementation steps including Micro-Architecture, RTL Coding, constraints generation/verification/review, Lint check, CDC check, DC Synthesis and PT Static Timing Analysis.
- Ability to develop clear and concise Engineering documents
- Ability to work with internal Verification Team for verifying the IP and Validation Team for bring-up.