ASIC Design Manager
Experience: 10 to 12 years
Qualification: B.E. / B. Tech in “Electronics” or “Electronics & Telecommunication”
Job Description: Front end digital design developing micro-architecture, RTL implementation, integration and verification, FPGA synthesis and timing analysis on Xilinx tools, debugging for functionality and resolving issues during FPGA/ASIC real time validation.
Roles & Responsibilities:
- Participated in at least one ASIC tape out. Knowledgeable of full chip cycle.
- Experience in design implementation involving micro-architecture development from specifications, developing synthesizable RTL modules using Verilog HDL, developing verification environment including models for unit level and top-level verification.
- Real time experience in debugging for functionality and resolving issues during FPGA/ASIC validation.
- Hands on experience on module level and top-level FPGA synthesis using Xilinx tools.
- Hands on experience on module level synthesis using Design Compiler.
- Prior experience working with Lab tools like Logic analyzer, USB and PCIe protocol analyzer is a plus.
- Prior experience with protocols such as PCIe, USB2.0/3.0, SATA is highly desirable.
- Prior experience working on ARM based SOC is desired.
- Exposure to DFT, Physical Design cycle
- Experience in simulation environment design, verification methodologies such as UVM/OVM, System Verilog is a plus.
- Coding skills in Perl, TCL/TK, or other industry-standard scripting languages
- Need to be a team player and have excellent communication skills. Highly focused, results-based approach to meet tight schedules.