ASIC RTL Design Engineer

Hyderabad, India -Full Time


5+ years


B.E. / B. Tech in “Electronics” or “Electronics & Telecommunication”

Roles & Responsibilities:

  • Worked on ASIC projects.
  • Knowledgeable of Full chip cycle.
  • Good understanding of Verilog (RTL), Digital design principles, Timing Constraints
  • Front End Design and Implementation steps including Micro-Architecture, RTL
    Coding, constraints generation/verification/review, Lint check, CDC check, DC Synthesis and PT Static Timing Analysis.
  • Ability to develop clear and concise Engineering documents
  • Ability to work with internal Verification Team for verifying the IP and Validation Team for bring-up.
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