ASIC/SoC Design

MosChip’s extensive ASIC design experience ranges from architecture to netlist. MosChip provides the seamless integration of digital and analog IP. Designs are optimized for internal bus performance and external high speed interfaces.


 Experience Summary

  • Spec to Netlist and Silicon validation
  • 20+ ASIC Tapeouts
  • First Pass Silicon Achievement
  • 100% On-Time Delivery
  • 100% Focused Consultants
  • FPGA to ASIC Translation
  • 40nm TSMCLP Design
  • 28nm TSMCLP verification (Testchip)
  • 55mn gate density Largest design

 Key Differentiators

  • Unique combination of Silicon & Systems
  • Product development experience
  • Outstanding Processes, templates, structures & checklist for scaling up
  • Robust Internal Design Flows
  • Low Power Design Expertise
  • In-house developed reusable Cores (USB2.0 & 3.0)
  • Early adopters of advanced ASIC Verification methodologies like VMM, OVM & UVM.
  • Developed Scalable, Configurable, & Reusable Verification test bench
  • Large Designs Exposure
  • Analog/Mixed Signal Expertise
  • Power Optimization Experience
  • Yield Enhancement Services

 SoC & ASIC Expertise

  • Standards and system level understanding
  • System Architecture, FPGA design, Pre and Post Silicon validations
  • ASIC design, integration, verification, synthesis, design closure, power and package analysis
  • Synopsys, Cadence, Magma flow
  • ARM9 & ARM Cortex based SoCs
  • General Purpose, Storage & Network SoCs
  • Multi Processor Cores
  • Video, Graphics & Processor Subsystems

Complete ASIC Design Capabilities

  • ASIC design, integration, verification, synthesis, design closure, power and package analysis, pre- and post-silicon validation.
  • Specification to Netlist
  • System architecture, FPGA design, pre- and post-silicon validation
  • Verilog, System Verilog, C/C++, Assembly, PLI/VPI, OVM/OVC and scripting
  • Developed Scalable, Configurable, & Reusable Verification test bench

Standards and system level Competencies

  • ARM, PCI, PCIe 1.1/2.0
  • USB 2.0, OTG, USB 3.0 (Internal IPs)
  • SATA  Host & Device Controller
  • Ethernet (10/100/1000), TCP offload Engines
  • Display controller, HDMI (Digital)
  • Storage Security: IEEE-P1619 compliant XTS-AES
  • IrDA, Serial Port, Parallel port
  • DMA controllers, I2C, SPI
  • External & internal Buss- ISA, AHB, APB, VCI, etc.
  • Memory Controllers & Interfaces – SRAM, DRAM, DDR/1/2, Flash

MOSCHIP infographics

ASIC Tools Expertise

  • Verilog & System Verilog
  • Cadence simulator – IUS8.2
  • Synopsis–DC for synthesis
  • Surelint by Verisity for Linting
  • Cadence-ICCR – Code coverage
  • Cadence simulator – NcVerilog
  • Xilinx ISE for FPGA validation
  • FPGA synthesis by Synplicity and Synlicity
  • Altera Quartus for FPGA synthesis
  • ARM tools

SoC Design Case Study

moschip ASIC Design